KR920004922B1 - Semiconductor integrated circuit device - Google Patents

Abstract

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Description

Semiconductor integrated circuit device

1 (a) and (b) are two input NOR circuit diagrams of the prior art;

2 is an inverter circuit diagram according to a first embodiment of the present invention.

3 is an inverter circuit diagram according to a second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly, to a BiFET semiconductor integrated circuit device in which a field effect transistor (FET) and a bipolar transistor are combined.

As a gate circuit combining a field effect transistor and a bipolar transistor, a two-input NOR gate circuit as shown in FIG. 1A is known (for example, IEEE Trans. Electron Devices, Vol. ED-16, No. 11, pp945 ~ 951, Nov. 1969).

This is a combination of NPNs 301 and 302 in a C-MOS transistor NOR gate circuit composed of PMOSs 200 and 201 and NMOSs 202 and 203 shown in FIG. 1B. However, in this two-input NOR gate circuit, NPN 301 is used. , 302 is a means for forcibly releasing the accumulated small charges, so that the time for the NPNs 301, 302 to be turned off becomes long. As a result, the state in which both the first and second NPNs 301 and 302 are turned on lasts for a long time, thereby increasing power consumption and delaying switching time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high speed and low power consumption semiconductor integrated circuit device, which is made up of the above-described BiCMOS composite circuit and is composed of a field effect transistor and a bipolar transistor.

In order to achieve the above object, in the semiconductor integrated circuit device of the present invention, the first bipolar transistor and the collector are connected to the output terminal side and the emitter is connected to the reference potential side, with the collector connected to the power supply side and the emitter connected to the output terminal side. An output circuit section including a second bipolar transistor, a logic inverting means having an output connected to a base of the first bipolar transistor in response to an input signal input to an input terminal, a drain connected to the output terminal, and a source connected to the second output terminal; A first field effect transistor connected to the base of the bipolar transistor and having a gate connected to the input terminal, and a second field effect disposed between the base and the reference potential of the second bipolar transistor and having a gate connected to the output of the logic inverting means. Base charge chamber of a second bipolar transistor comprising a transistor And means.

In a bipolar MOS composite circuit in which an output stage is constituted by a bipolar transistor, a logic is adopted as a MOS transistor, and a circuit for driving a bipolar transistor is provided, an element for releasing accumulated charge from the transistor when the bipolar transistor is turned off is provided. As a result, the bipolar transistor can be turned off quickly and the through current can be reduced, so that a high speed, low power consumption bipolar MOS composite circuit can be obtained.

Other objects and features of the present invention will become apparent from the following description of the embodiments.

Next, this invention is demonstrated concretely based on an Example.

2 shows an inverter circuit as a first embodiment of the present invention.

In FIG. 2, reference numeral 14 denotes a first NPN bipolar transistor (hereinafter referred to as first NPN) in which collector C is connected to power terminal 1 having a first fixed potential and emitter E is connected to output terminal 17. In FIG. 15 is a second NPN bipolar transistor (hereinafter referred to as a second NPN) in which the collector C is connected to the output terminal 17 and the emitter E is connected to the ground potential GND, which is the second fixed potential. ), 10 is a P-type insulated gate electric field in which the gate G is connected to the input terminal 16 and the source 5 and the drain D are connected to the collector C and the base B of the first NPN, respectively. In the effect transistor (hereinafter referred to as PMOS), 11, the gate G is connected to the input terminal 16, and the drain D and the source S are connected to the collector C and the base B of the second NPN. N-type insulated gate field effect transistor (hereinafter referred to as NMOS). In addition, 90 is a 2N type insulated gate field effect transistor (hereinafter referred to as a second NMOS), and the gate G of the second NMOS 90 is connected to the input terminal 16 and has a drain D and a source S. Are connected to the drain D of the PMOS 10 and the base B of the NPN 15, respectively. 110 is an N-type insulated gate field effect transistor (hereinafter referred to as a third NMOS), and the gate G of the third NMOS 110 is connected to the base B of the first NPN 14 and to the drain D. And the source S is connected to the base B and the emitter E of the second NPN 15. The PMOS 10 and the NMOS 90 constitute a logic inverting means of the input signal input to the input terminal 16.

Table 1 shows the second logical operation of this embodiment.

TABLE 1

When input 16 is at " 0 " level, PMOS 10 is on and NMOS 90, 11 is off. Therefore, the first NPN 14 is turned on. At this time, since the NMOS 11 is turned off, the supply of current to the second NPN 15 is stopped and the accumulated charge accumulated in the base B and the NMOS 11 of the second NPN 15 is turned on. The second NPN 15 is rapidly turned off because it is emitted via the NMOS 110. Therefore, the emitter current of the first NPN 14 charges the electric charge so that the output 17 rapidly reaches the " 1 " level.

When the input 16 is at the " 1 " level, the PMOS 10 is turned off, and the first NMOS 11 and the second NMOS 90 are turned on. At this time, the PMOS 10 is turned off. As a result, the supply of current to the first NPN 14 is stopped and discharged via the second NMOS 90 at which the storage charge accumulated in the base B of the first NPN 14 and the PMOS 10 is turned on. Therefore, the first NPN 14 is rapidly turned off. In addition, since the NMOS 11 is turned on and the drain D and the source S are short-circuited, the base B of the second NPN 15 has a current from the output 17 and the above-mentioned All of the electric charges stored in the base B and the PMOS 10 of the first NPN 14 are supplied, so that the second NPN 15 is rapidly turned on. Therefore, the output 17 rapidly goes to the "0" level.

Next, the operation of the third NMOS 110 will be described in detail. When the NMOS 11 and the second NPN 15 are switched from on to off, that is, when the input 16 goes from "1" to "0" level, the second NMOS 11 and the second NPN 15 The accumulated charge accumulated in the base B of the C) is discharged through the third NMOS 110 which is turned on. When the input 16 is at the " 0 " level, the high base potential of the first NPN 14 (same as the power supply potential) is added to the gate of the third NMOS 110 so that the third NMOS 110 is turned on so that the third NMOS 110 is turned on. 2 Short-circuits between the base and the emitter of the NPN 15 releases accumulated charge at high speed.

On the other hand, when the input 16 goes from "0" to "1" level, the low base potential of the first NPN 14 is added to the gate of the third NMOS 110 so that the third NMOS 110 is turned off. Therefore, since the current supplied to the base B of the second NPN 15 does not flow toward the NMOS 110, sufficient base current is supplied to the second NPN 15 so that the second NPN 15 is rapidly turned on. do.

Therefore, the NMOS 110 rapidly turns on and off the NPN 15 in response to an input signal, thereby obtaining a BiCMOS circuit of high speed and low power consumption.

3 shows an inverter circuit as a second embodiment of the present invention. This circuit has a configuration substantially the same as that of the embodiment shown in FIG. 2 and is similar in operation.

In FIG. 3, the same code | symbol as 2nd degree has shown the same and equivalent. Unlike the circuit of FIG. 2, the first and second NPNs 14 and 15 of FIG. 2 are replaced with the transistors 125 and 126 with Schottky barrier diodes, respectively, and the base current supply of the second NPN 126 is performed. As a result, the fourth NMOS 123 is provided.

According to this embodiment, an inverter circuit which is higher speed than that of the first embodiment can be realized.

As described above, according to the present invention, a high speed, low power consumption semiconductor integrated circuit device combining a field effect transistor and a bipolar transistor can be obtained.

Claims (1)

An output circuit section including a first bipolar transistor having a collector connected to a power supply side and an emitter connected to an output terminal side, and a second bipolar transistor connected to an output terminal side and a collector connected to an emission reference potential side; Logic inverting means, the output of which is connected to the base of the first bipolar transistor in response to an input signal input to the input terminal; A first field effect transistor having a drain connected to the output terminal, a source connected to a base of a second bipolar transistor, and a gate connected to the input terminal; And a base charge emitting means of a second bipolar transistor, which is provided between the base of the second bipolar transistor and the reference potential, and includes a second field effect transistor whose gate is connected to the output of the logic inverting means. Semiconductor integrated circuit device.