JPS6388916A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quicken the speed of a Bi-CMOS circuit by providing a MOS transistor (TR) between the output terminal of a CMOS logic circuit and the output terminal of a bipolar TR being an output stage. CONSTITUTION:When the level of a input terminal 11 or 12 goes to L, a PMOS 101 or 02 is turned on and an NMOS 103 or 104 is turned off. Then the NMOS 105 is turned on and the PMOS 301 is turned off, then the TR 201 is turned on and the TR 202 is turned off, and the output terminal 31 goes to H. When both the input terminals 11 and 12 go to H, the PMOS 101 and 102 are turned off and the NMOS 103 and 104 are turned on. As the stored charge at a node N11 is discharged through the NMOS 103, 104 and 105, the NMOS 105 is turned off and the PMOS 301 is turned on. Then the electric charge stored in the load turns on the TR 202 through the PMOS 301, NMOS 103, 104 and the output terminal 31 goes to L. Since a conventional dode is replaced into the PMOS 301, high speed is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit configuration of a semiconductor integrated circuit using complementary MO8 transistors and bipolar transistors.

[Conventional technology]

Conventionally, an example of a semiconductor integrated circuit characterized by comprising a bipolar transistor constituting this type of output stage and a complementary MO8 transistor that drives the bipolar transistor and provides logic is shown in FIG.

Hereinafter, such a semiconductor integrated circuit will be referred to as a Bi-0M08 circuit.

101 is a P-type MO8 transistor whose source is connected to the power supply potential, its gate is connected to the input terminal 11, and its drain is connected to the node Nil; 102 is a P-type MO8 transistor whose source is connected to the power supply potential, its gate is connected to the input terminal 12, and its drain is connected to the node Nil. P-type MO
8 transistor 103 has a source connected to node N12, a gate to input terminal 11, and a drain to node Nil.
104 is an N-type hiO8 transistor whose source is connected to the node N13, its gate is connected to the input terminal 12, and its drain is connected to the node N12. 105 is an N-type MOS transistor whose source is connected to the ground potential and whose gate is connected to the node N13. , 201 is N whose collector is connected to the power supply potential, whose base is connected to the node Nil, and whose emitter is connected to the output terminal 31.
A PN bipolar transistor, 2o2, is an NPN bipolar transistor whose collector is connected to the output terminal 31, and whose emitter is connected to the ground potential at the base node N13, 4o1.
is a diode whose anode is connected to the output terminal 31 and whose cathode is connected to the node Nil.

Next, the operation of this circuit will be described.

Now, when the level of at least one of the input terminals 11 and 12 becomes LOW, the P-type MOS transistor 1
At least one of 01 and 102 is turned on and N type M
At least one of the OS transistors 103 and 104 is cut off.

This K is connected to the power supply potential of the node N11Fi and becomes an H level, and the N-type MOS transistor 10
5 turns on. At this time, diode 401 is reverse biased and functions as a capacitor. P type M in on state
At least one of the O8 transistors 101 and 102 is connected to the NPN bipolar transistor 201.
When the base current is supplied, the NPN type bipolar transistor 201 is turned on and supplies current to the output terminal 31.

On the other hand, the NPN bipolar transistor 202 is an N-type M
The OS transistor 105 connects the base to the ground potential and is cut off.

As a result of the above, the output terminal 31 becomes H level.

Next, when input terminals 11 and 12 both become Hi level, P
Both type MOS transistors lo1 and 102+5f are cut on, and N type MOS transistors 103 and 104 are turned on. From this button, the charge accumulated in the load is
A base current of the NPN bipolar transistor 202 is supplied from the output terminal 31 side through a diode 401 and N-type MOS transistors 103 and 104 in series.

This turns on the NPN bipolar transistor,
The charge accumulated in the load becomes a collector current of the NPN bipolar transistor 202 and is drawn to the ground potential.

When the output terminal 310 level decreases, the node N11°Nl 2
, Nl 3 are also lowered in level, the NPN type bipolar transistor 201 is cut off, and the N type MOS transistor 105 is also cut off.

Therefore, the level of the output terminal 31 continues to decrease, and the charge accumulated in the load decreases until the collector current and base current of the NPN bipolar transistor 202 can no longer be supplied, and becomes LOW level.

[Problem that the invention seeks to solve]

The conventional Bi-0M08 circuit described above obtains the output of the logic gate by the switching operation of the bipolar transistor connected to the totem pole, but when the output of the logic gate shifts from the Hi level to the LOW level, it accumulates in the load. The base current of the bipolar transistor that drives the LOW level side is supplied through the diode as the base current of the bipolar transistor that drives the LOW level side, which causes a delay in the forward rise time of the diode and a forward voltage drop of the diode. (is small)) Sufficient driving is not performed, and the falling time of the output of the logic gate becomes long. Also, when the output of the logic gate shifts from the LOW level to the H level, the base current of the bipolar transistor that drives the H1 side is bypassed to the output side by the diode that acts as a capacitor and becomes small, resulting in a longer rise time. There is a drawback.

[Failure to solve the problem]

The semiconductor integrated circuit of the present invention includes a bipolar transistor forming an output stage of a logic gate, and a complementary MO for driving the bipolar transistor in the output stage and providing logic.
Complementary MO8 in a logic circuit consisting of 8 transistors
A MOS transistor is provided between the logic output terminal of the transistor and the output terminal of the bipolar transistor forming the output stage of the logic gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a two-manpower NAND gate according to an embodiment of the present invention.

11.12 is an input terminal, 21 is a power supply terminal, 31 is an output terminal, 101 has a source at power supply potential, and a gate at input terminal 1.
1 is a P-type MO8 transistor whose drain is connected to the node Nil; 102 is a P-type MO8 transistor whose source is connected to the power supply potential; its gate is connected to the input terminal 12; and its drain is connected to the node NIIK; 103 is a P-type MO8 transistor whose source is connected to the node N12. An NfiMO8 transistor whose gate is connected to the input terminal 11 and whose drain is connected to the node Nil, and the source of 104 is connected to the node Nil.
13 is an N-type MO8 transistor whose gate is connected to the input terminal 12 and its drain is connected to the node N12; 105 is an N-type MO8 transistor whose source is connected to the ground potential, 1 gate is connected to the node NI IK, and the drain is connected to the node N13; 201 is an NPN type bipolar transistor whose collector is connected to the power supply terminal, one pace is connected to the node Nil, and the emitter is connected to the output terminal 31. 202 is an NPN whose collector is connected to the output terminal 31, the pace is connected to the node N13, and the emitter is connected to the ground potential. type bipolar transistor, 301 has a source connected to output terminal 3
1 is a P-type MO8 transistor whose gate is connected to node Nil and whose drain is connected to node Nil.

Next, the operation of this embodiment will be described.

If the level of at least one of the input terminals 11 and 12 is now LOW, the P-type MO8 transistor 10
At least one of 1 and 102 is turned on, and the N type M
At least one of O8 transistors 103 and 104 is cut off.

As a result, the node Nil is connected to the power supply potential and becomes HI level.
l, P-type MO8301 cut-off.

P-type MO8 transistor 101°102 in on state
A pace current is supplied to the NPN bipolar transistor 201 from at least one of the transistors, and the NPN bipolar transistor 2C1 is turned on, supplying current to the output terminal 31.

On the other hand, the NPN type bibor 2 transistor 202 is N1M0
The eight transistors 105 cut off by connecting the paste to the ground potential.

As a result of the above, the output terminal 31 becomes H level.

Next, when input terminals 11 and 12 both go to Ki level, the P-type MOS is turned on? registers 101 and 102 are cut off, and N
The MO8 type MO8 transistors 103 and 104 are turned on.

At this time, the N-type MO8 transistor 105 is in the on state, and the P
The type MO8 transistor 301 is in an off state.

The charge accumulated at node N11 is transferred to N-type MO8103,
104 and 105 in series to the ground potential,
The potential of the node Nil decreases.

Then, the N-type MO8 transistor 105 is gradually cut off, the P-type MO8 transistor 301 is gradually turned on, and the NPN-type bipolar transistor 201 is also gradually cut off.

As a result, the charge accumulated in the load is transferred to the output terminal 31.
The base current of the NPN bipolar transistor 202 is supplied from the side via a P-type MO8 transistor 301 and N-type MOS transistors 103 and 104 in series.

Then, the NPN type bipolar transistor 202 is turned on, and the charge accumulated in the load is extracted to the ground potential.

As a result, when the level of the output terminal 31 decreases, the node Ni
l, N12. Since the level of N13 also decreases, the NPN type bipolar transistor 201 is completely cut off, and the NPN bipolar transistor 201 is completely cut off.
The type MO8 transistor 105 is also completely cut off.

As a result, the level of the output terminal 31 continues to fall, and the charge accumulated in the load drops to the LOW level when the collector current and base current of the NPN bipolar transistor can no longer be supplied.

As described above, according to this embodiment, it is possible to configure a Bi-CMO8 logic gate using only complementary MO8 transistors and a pie-borer transistor.
This is an embodiment in which a -0 MO8 logic gate has an N-type MO8 transistor between the logic output terminal of a complementary MO8 transistor and the output terminal of a bipolar transistor constituting the output stage of the logic gate.

In addition, the Bi-CMO8 circuit of this system shown in Figs. 1 and 3 also uses complementary type M
This is especially possible by changing the structure of the O8 transistor, and the N-type MOS transistor 105 shown in this embodiment can be replaced with a resistor.

〔Effect of the invention〕

As explained above, the present invention is applicable to conventional Bi-CMO
In the S semiconductor integrated circuit, an M is connected instead of a diode between the logic output terminal of the complementary MO8 transistor and the output terminal of the bipolar transistor constituting the output stage of the logic gate.
By having an OS transistor, it is possible to basically eliminate the forward voltage drop and the operation as a capacitance during reverse bias, which the diode of the conventional method has, so high-speed power logic operation is possible. There is no need to create a diode on the outside, and the circuit can be realized by using one more MOS transistor. Moreover, the MOS transistor used in place of the diode is a complementary type M that takes logic.
This has the advantage that it can be easily manufactured as a MOS transistor having the active region of the O8 transistor in common.

[Brief explanation of the drawing]

Figure 1 shows the P-type MOS transistor of the present invention. B1- using register
A circuit diagram of a CMO82 human-powered NAND gate, FIG. 2 is a circuit diagram of a 9-Bi-CMO82 human-powered NAND gate using conventional diodes, and FIG. 3 is a circuit diagram of a Bi-CMO82 human-powered NAND gate using an N-type MOS transistor of the present invention. FIG. 4 is a layout and contact pattern diagram of one embodiment of the circuit diagram shown in FIG. 1 of the present invention. 11...Input terminal, 12...Input terminal, 1o1...P-type MOS transistor, 102
・Old...PWMOS transistor, 103...
N-type MOS transistor, 104...N-type MO
S transistor, 105...N-type MOS transistor, 2o1, old...NPN-type bipolar transistor, 2o2...NPN-type bipolar transistor, 301...P-type MO8): 7 Njista, 3
02...N-type MOS transistor, 401...
...Diode, N11...Node, N12
...Node, N13...Node, Work...
...P-type MO8 transistor area, ■...N
type MOS transistor region, ■... Bipolar transistor region, ■... Bipolar transistor region, 21... Power supply terminal, 31...
・Output terminal, 501... Drain of P-type MO8 transistor 101, 502... Same goo), 5
03... Same source and source of P-type MOS transistor 102, 504... Gate of P-type MOS transistor, 505... Same drain and P-type MOS transistor 102...
type MOS transistor 301 drain, 506...
...Gate of P-type MO8 transistor 301, 507
...Same source, 601...N type MOS
Drain of transistor 103, 602... same goo), 603... same source and drain of N-type MOS transistor 104, 604... gate of N-type MOS transistor 104, 605・・・・・・
・Same source and drain of N-type MOS transistor 105, 606... N-type MOS transistor 105
gate, 6o7...same source, 7o1...
... Collector of NPN type bipolar transistor 201, 702 ... Emitter of same, 7o3 ...
・Same pace, 801...NPNfJ, <collector of a polar transistor, 802...same construction, 8o3...-flli] Base, and the vertical stripes indicate aluminum It's the wiring. 2nd time

Claims (1)

[Claims] In a logic circuit consisting of a bipolar transistor that constitutes the output stage of a logic gate and a complementary MOS transistor that drives the bipolar transistor of the output stage and provides logic, the logic output end of the complementary MOS transistor and the output stage of the logic gate are connected. A semiconductor integrated circuit characterized by having a MOS transistor between an output terminal of a bipolar transistor constituting the circuit.