JPH10256483A - Mos semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily realize a circuit which can generate a desired bias potential by using a diode circuit instead of a MOD transistor circuit in a CMOS circuit board. SOLUTION: An N-type diffusion area 2 is formed in a P-type semiconductor substrate 1 having a 0-V bias and a P-type diffusion area 3 is formed in the diffusion area 2. An N-type diffusion area 4 having an impurity concentration for a Schottky barrier which can operate as a rectifier element is formed in the diffusion area 3 and a metallic electrode 5 for Schottky junction is provided on the diffusion area 4 in a state where the electrode 5 is in contact with the area 4. N<+> and P<+> have impurity concentrations which are sufficient to obtain an ohmic contact with a metal. The diffusion areas 4 and 3 are short-circuited at the same potential. The N-type diffusion area 2 is connected to a voltage (for example, Vcc) higher than 0V. This constitution is formed in an CMOS circuit (11 or 12).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a circuit configuration for providing a forward diode on a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 5A shows a negative potential boosting circuit (charge pump circuit) formed in a MOS type semiconductor integrated circuit.
1 shows a general circuit diagram of FIG. The current path is connected to the output terminals OUT and 0
V, MOS transistors M1, M2, and M3 each having a gate and a drain connected to each other;
It is composed of capacitors C1 and C2 inserted between the connection node between the S transistors and the pulse input terminal.
The back gate (well region bias) is connected to a positive power supply voltage Vcc.

When a complementary pulse signal as shown in FIG. 5 (b) is input to each of the pulse input terminals,
The MOS transistor transfers the positive charge at the output terminal OUT in the direction in which M1, M2 and M3 are arranged. As a result, the output terminal OUT generates a negative potential, but the positive charge transfer is limited by the threshold voltage of each MOS transistor.
In addition, this threshold voltage increases the charge transfer loss as the source potential of the MOS transistor decreases.

[0004]

Conventionally, a circuit for generating a negative bias potential provided in a MOS-type semiconductor integrated circuit includes a circuit in which MOS transistors are connected in series, and the efficiency of charge transfer depends on each MOS transistor. This is undesirably limited by the threshold voltage.

The present invention has been made in view of the above circumstances, and has as its object to provide a circuit for generating a desired bias potential using a diode circuit instead of a MOS transistor circuit.
An object of the present invention is to provide a MOS semiconductor integrated circuit formed in a MOS circuit substrate.

[0006]

A CMOS type semiconductor integrated circuit according to the present invention has a P-type semiconductor substrate, and at least one electrode formed on the semiconductor substrate, which is forward-biased to the semiconductor substrate and at least one electrode has a substrate potential. A Schottky barrier diode set at a low potential and a MOS transistor formed on the semiconductor substrate.

According to the present invention, a rectifying element which does not suffer from an operation failure due to a parasitic bipolar element even when a negative potential and a forward bias are applied to both ends is obtained by utilizing a generally performed double well structure.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION In a circuit for generating a negative bias potential, consider the use of a diode circuit instead of a MOS transistor configuration limited by a threshold voltage. For example, FIG. 6 shows a negative potential boosting circuit including a series circuit of diodes D1, D2 and D3 corresponding to the configuration of FIG.

However, when such a diode is provided on a P-type semiconductor substrate, an N-type region is lower than the substrate potential, and a forward-biased PN junction diode is used to prevent a parasitic bipolar transistor from operating. The formation requires a triple well structure as shown in FIG. This structure is very complex and is too costly to implement at present. Thus, in the present invention, a diode to which a negative bias is applied to one end is referred to as a CM.
Provided is a configuration that can be easily realized in an OS circuit board.

FIG. 1 is a sectional view showing a configuration of a MOS type semiconductor integrated circuit including a diode circuit according to a first embodiment of the present invention. The P-type semiconductor substrate 1 is biased to 0V. An N-type impurity diffusion region (N-well region) 2 is formed on a substrate 1. In the N-type impurity diffusion region 2, a P-type impurity diffusion region (P well region) 3 is formed. An N-type impurity diffusion region 4 is formed in the P-type impurity diffusion region 3.

The N-type impurity diffusion region 4 has an impurity concentration for a Schottky barrier operable as a rectifying element, and the impurity concentration is set to 10 ¹⁸ / cm ³ or less. The metal electrode 5 for Schottky contact in contact with the N-type impurity diffusion region 4 is made of Al, Ti, TiSi ₂ or the like.

Further, N ⁺ and P ⁺ in the figure have an impurity concentration sufficient to make ohmic contact with a metal. N-type impurity diffusion region 4 and P-type impurity diffusion region 3
Are shorted to the same potential. The N-type impurity diffusion region 2 is connected to a voltage higher than 0 V (for example, a power supply Vcc).

On the substrate 1, a CMOS circuit and the like are additionally formed. On the substrate 1, an N-channel MOSFET 11 is formed. An N-well region 6 formed in the same step as the N-type impurity diffusion region 2 has a P-channel MOSFET 12
Is formed. An N-channel MOSFET is provided in a P-well region 7 formed in the same process as the P-type impurity diffusion region 3.
13 is formed.

According to the above structure, a rectifying element free from operation failure due to a parasitic bipolar element even when a negative potential and a forward bias are applied to both ends in a process generally performed using a double well structure. Can be.

FIG. 2 is a block diagram showing a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a negative potential boosting circuit configured in the OS type semiconductor integrated circuit. The negative potential booster circuit is called a charge pump circuit, and is provided, for example, to generate an operation power supply voltage in a memory circuit. Each of the Schottky barrier diodes SBD1, SBD2, S is connected between the output terminal OUT and 0V.
BD3 is connected in series with a forward bias. Capacitors C1 and C2 are inserted between the connection node between the two Schottky barrier diodes and the pulse input terminal.

A complementary signal (similar to that shown in FIG. 5 (b)) which oscillates between the ground potential and the positive power supply potential is applied to the pulse input terminals of the capacitors C1 and C2, so that the diodes SBD1, SBD2 and SBD3 are turned off. Output end O in line in the forward direction
Transfers positive charges on the UT side. Thereby, the output terminal OUT
Generates a negative potential. Positive charge transfer is only loss of forward bias voltage of each diode, high efficiency,
A high-voltage negative potential boosting circuit can be formed.

FIG. 3 shows a part of FIG.
FIG. 3 is a cross-sectional view illustrating a configuration of a barrier diode and a capacitor. The capacitor (here, C2) is constituted by a MOS capacitor. In the Schottky barrier diode unit, the same parts as those in FIG.

FIG. 4 is a circuit diagram showing a constant voltage generating circuit according to a third embodiment of the present invention. 0V and output terminal OU
A Schottky barrier diode SBD4 is connected in the forward direction between T and T. The output terminal OUT is connected to the negative potential _VEE via the resistor R. According to such a configuration,
Depending on the concentration of the substrate, the metal material in contact with the substrate as an electrode, and the number of diodes connected in series, a negative constant potential corresponding to the bias voltage of the Schottky barrier can be obtained.

In the above-described embodiment, a configuration in which a Schottky barrier diode circuit is provided on a P-type semiconductor substrate and a negative potential is generated from a ground potential and a positive power supply potential higher than the ground potential has been described. A Schottky barrier diode circuit may be provided on a semiconductor substrate to generate a voltage higher than the power supply potential from the ground potential and a power supply potential higher than the ground potential.

[0020]

As described above, according to the present invention,
Utilizing the process of the double well structure generally performed,
It can be configured according to the manufacturing process of the CMOS circuit,
Even if a negative potential and a forward bias are applied to both ends, a rectifying element free from operation failure due to a parasitic bipolar element can be obtained. In addition, this rectifier element, that is, a Schottky barrier diode can be applied as a charge transfer means on a P-type substrate, and a CMO provided with a high-efficiency, high-voltage negative potential booster circuit is provided.
An S-type semiconductor integrated circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a MOS semiconductor integrated circuit including a diode circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a negative potential boosting circuit configured in a MOS semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a part of FIG. 2 and showing a configuration of a Schottky barrier diode and a capacitor.

FIG. 4 is a circuit diagram showing a constant voltage generation circuit according to a third embodiment of the present invention.

FIG. 5A is a general circuit diagram of a negative potential boosting circuit (charge pump circuit) configured in a MOS semiconductor integrated circuit. (B) is a waveform diagram of a complementary pulse signal supplied to a pulse input terminal.

FIG. 6 is a circuit diagram showing a negative potential boosting circuit including a series circuit of diodes corresponding to the configuration of FIG. 5A.

FIG. 7 is a sectional view of a part of the diode in FIG. 6;

[Explanation of symbols]

 1 P-type semiconductor substrate 2 N-type impurity diffusion region (N-well region) 3 P-type impurity diffusion region (P-well region) 4 N-type impurity diffusion region 5 Metal electrode 6 N-well region 7 ... P-well regions 11 and 13... N-channel MOSFET 12... P-channel MOSFET SBD1 to 3.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H02M 3/07

Claims (6)

[Claims] A P-type semiconductor substrate; a Schottky barrier diode formed on the semiconductor substrate, wherein the Schottky barrier diode is forward-biased to the semiconductor substrate and at least one electrode is set at a potential lower than the substrate potential; And a MOS transistor formed on the semiconductor substrate. 2. The MOS type according to claim 1, wherein the Schottky barrier diode is included in a part of a charge pump circuit that generates a negative potential from a ground potential and a positive power supply potential higher than the ground potential. Semiconductor integrated circuit. 3. The MOS semiconductor integrated circuit according to claim 1, wherein said Schottky barrier diode is used in a circuit for generating a reference potential. 4. An N-type semiconductor substrate; a Schottky barrier diode formed on the semiconductor substrate, wherein the Schottky barrier diode is forward-biased to the semiconductor substrate and at least one electrode is set to a potential higher than the substrate potential; And a MOS transistor formed on the semiconductor substrate. 5. The MOS type according to claim 4, wherein said Schottky barrier diode is included in a part of a circuit for generating a voltage higher than a power supply potential from a ground potential and a power supply potential higher than the ground potential. Semiconductor integrated circuit. 6. The MOS semiconductor integrated circuit according to claim 4, wherein said Schottky barrier diode is used in a circuit for generating a reference potential.