KR920003855B1 - Frequency variable pwm signal generating circuit - Google Patents

Abstract

The PWM signal generator adjusts the pulse width of PWM signal precisely using a clock signal generator in place of a ripple counter and generates high frequency PWM signals having fast response characteristics to system clock signal using logic gates. The PWM signal generator comprises a latch unit (10) for latching the counted value (CR) of a main counter, a clock signal generator (30) for generating clock signals having various frequencies by receiving system clock (fc), and a PWM signal output stage (20) for generating and outputting PWM signals according to N- bit output signal of the latch unit (10) and clock signals (CC6- CC15) of the clock signal generator (30).

Description

Frequency Variable Variable PWM Signal Generation Circuit

1 is a conventional pulse width modulated signal (PWM signal) generating circuit.

FIG. 2 is a waveform diagram of each part of the conventional PWM signal generating circuit shown in FIG.

3 is a block diagram of a frequency variable PWM signal generating circuit of the present invention.

4 is a detailed circuit diagram of a clock generation unit in the convexity of the present invention shown in FIG.

FIG. 5 is a waveform diagram of each part of the clock generator shown in FIG.

6 is a detailed circuit diagram of a PWM signal output unit in the block diagram of the PWM signal generating circuit of the present invention shown in FIG.

FIG. 7 is a waveform diagram of each part of the PWM signal output unit shown in FIG.

* Explanation of symbols for main parts of the drawings

1, 10: latch circuit 2, 20: PWM signal output

3: ripple counter 30: clock generator

C: Counter part L: Logic circuit part

LC: Logic Circuit CR: Counting Signal

SS: Sampling signal f _c : System clock

CK, CC1 to CC17: Clock signal AD1 to ADN: And gate

NR1 ~ NR3: Noah gate FF: Flip-flop

The present invention relates to a pulse width modulated signal (PWM) generation circuit, which is an output signal of a servo system, and in particular, by using a clock generator and a logic circuit instead of a ripple counter, the accuracy of the PWM signal can be increased and the frequency can be increased. A frequency variable PWM signal generating circuit for generating a PWM signal having a fast response speed.

In general, in the servo system that controls the speed and phase of the motor, the motor drive part which outputs the speed and phase control result of the motor as a pulse width modulation signal (hereinafter referred to as PWM signal), passes through a low pass filter, and then drives the motor. The conventional PWM signal generation circuit for generating such a PWM signal is configured as shown in FIG. That is, in the conventional PWM signal generation circuit composed of the latch circuit section 1, the PWM signal output section 2, and the ripple counter 3, the count value CR counted at the main counter (not shown) is transferred to the latch circuit section 1. When applied, the applied count value CR is latched. This latch operation is performed according to the sampling signal SS applied to the latch circuit unit 1. On the other hand, the ripple counter 3 that counts the input clock signal CK and outputs an N-bit counting signal is full counting (in the waveform diagram shown in FIG. 2, the signal 2-1 is a ripple counter ( The output waveform of 3) is the time t _l in the case of full counting.) Noah gate (NR2) in the PWM signal output section 2 since the output of the most significant bit from the most significant (MB) becomes the low level. The output REF of is in the lower state (signal (2-2) in FIG. 2). At this time, that is either the output of the output ripple counter 3 is not equal to the output AND gates (AD1 ~ ADN) in the PWM signal output unit (2) of the second degree latch circuit (1) from t _l is high Since the COM signal, which is the output of the NOA gate NR1 (signal (2-3) in FIG. 2), is in the low level state, the output PWM of the flip-flop FF becomes low level. (2-4) signal. Subsequently, at the time t _{2 at} which the output of the latch circuit 1 becomes equal to the output of the ripple counter 3, the outputs of the AND gates AD1 to ADN are all at a low level, so that the output of the NOA gate NR1 is COM. Since the signal (signal (2-3) in FIG. 2) becomes high level, output PWM of flip-flop FF becomes high level ((2-4) signal). Thereafter, even though the level of the COM signal is changed several times by the outputs of the latch circuit 1 and the ripple counter 3, the output signal PWM maintains a high level due to the characteristics of the flip-flop FF. The frequency of 2-4) is determined by the full counting time of the ripple counter 3, and the pulse width of the PWM signal 2-4 changes according to the output of the latch circuit unit 1. Therefore, when the value SS of the sampling signal applied to the latch circuit unit 1 is small, the PWM signal 2-4 as shown in FIG. 2A is outputted, and when it is large, the PWM signal 2 as shown in FIG. 2C as shown in FIG. -4) is output.

When the PWM signal 2-4 outputted in such an operation passes through the low pass filter, it cannot exhibit a sufficient output change with respect to the precise control amount. That is, since the pulse width of the PWM signal is determined by the single frequency of the sampling signal SS, the pulse width of the PWM signal cannot be changed precisely, and the frequency of the PWM signal determined by the counting time of the ripple counter is not high. Therefore, there is a drawback that a delay time is required for the instantaneous change of the output of the latch circuit portion to be reflected in the PWM signal.

The present invention is designed to solve the above disadvantages of the conventional PWM signal generating circuit, and can accurately change the pulse width of the PWM signal by using a clock generator that outputs a clock signal having various frequencies instead of the ripple counter. The purpose of the present invention is to provide a frequency variable PWM signal generating circuit that generates a PWM signal with a high response time by obtaining a high frequency PWM signal by configuring the signal output part as a logic gate without using flip-flops. .

The present invention for achieving the above object is a PWM signal generating circuit having a latch circuit portion 10 for latching a counting value (CR) output from a main counter (not shown), the system clock (f _c ) as an input A clock generator 30 comprising a counter part C and a logic circuit part L for generating clock signals of various frequencies; PWM signal output section 20 composed of a logic circuit (LC) for outputting a PWM signal by inputting the clock signal (CC6 ~ CC15) of the N-bit output of the latch circuit section 10 and the output of the clock generator 30. It is composed of

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of the present invention, FIG. 4 is a detailed circuit diagram of the clock generator 30 shown in FIG. 3, FIG. 5 is a waveform diagram of a clock signal output from the clock generator 30, and FIG. A detailed circuit diagram of the PWM output unit 20, FIG. 7 is an input / output signal waveform diagram of the PWM output unit 20. Referring first to FIG. 3, the counting value CR from the main counter (not shown) is latch circuit unit 10. FIG. When the set signal S and the system clock f _c are applied to the clock generator 30, the latch circuit unit 10 latches the input counting value CR. The clock generator 30 divides the input system clock f _c , and the division operation of the clock generator 30 is performed by the circuit shown in FIG. 4.

)를 출력하게 된다. 카운터부(C)로부터 출력되는 출력신호(Q,

)는 논리회로부(L)로 인가되어 논리회로부(L)에 있는 논리게이트들에 의해 논리조합되어 출력되는바, 이렇게하여 논리회로부(L)로부터 출력되는 클럭신호(CC6~CC15)는 제 5 도에 도시한 바와 같이 시스템클럭(f_c)을 각각 N분주한 클럭신호로 된다. 제 5 도에 있어서, 두 클럭신호(CC11)가 존재하고 있는바, 이는 아래에 있는 클럭신호(CC12~CC15)는 클럭신호(CC6)를 기준으로 하면, 도면상에 도시하기가 곤란하기 때문에 아랫쪽에 있는 클럭신호(CC11)를 가정하고, 클럭신호(CCI2~CC15)를 도시한 것이다. 이어 논리회로부(L)로부터 출력되는 클럭신호(CC12~CC15), 즉 클럭발생부(30)의 출력은 PWM출력부(20)로 인가되고, 래치회로부(10)에 래치되어 있던 주카운터의 카운팅값(CR)이 샘플링신호(SS)의 인가에 따라 PWM출력부(20)로 인가되는데, PWM출력부(20)의 앤드게이트(AD1~AD10)중 래치회로부(10)의 하이레벨출력이 인가되는 앤드게이트만이 클럭발생부(30)의 출력인 클럭신호를 출력하게 된다.(래치회로부(10)의 출력이 하이레벨로 되는 앤드게이트만이 클럭발생부(30)의 클럭신호를 그대로 출력하게 된다.) 이어 앤드게이트(AD1~AD10)의 출력이 노아게이트(NR1-NR3)를 거쳐 제 7 도에 도시한 바와 같은 클럭신호(W1~W3)로서 출력되며(도면에서 클럭신호(W3)는 주파수가 매우 낮아 도면상에 나타나지 않으므로 가상하여 도시한 것이다.) 클럭신호(W1~W3)가 낸드게이트(ND1)를 거쳐 제 7 도에 도시한 바와 같은 PWM신호로 출력되게 되는데, 제 7 도는 래치회로부(10)로 인가되는 카운팅값이 800으로 "0000010011"(LSB→MSB)일때의 클럭신호(CC6~CC10)와 클럭신호(W1~W3) 및 PWM 신호의 파형을 도시한 것으로, 제 7 도에서 보는 바와 같이 PWM 신호는 래치회로부(10)의 출력에 따라 클럭발생부(30)에서 출력되는 여러 클럭신호가 논리조합된 신호로 되기 때문에 펄스폭의 변화는 극도로 정밀하게 되고, 주파수 또한 정밀하게 변화하게 된다.That is, when the system clock f _c is inverted through the inverter IN and applied to the counter unit C, and a set signal S is applied from the ROM, the counter unit C is a system clock that is an input signal. Counting (f _c ), n types (n = 11 in FIG. 4) output signals Q,

) Will be printed. The output signal Q, output from the counter section C,

) Is applied to the logic circuit section L and is logically combined and output by the logic gates in the logic circuit section L. Thus, the clock signals CC6 to CC15 output from the logic circuit section L are shown in FIG. As shown in FIG. 2, clock signals obtained by dividing the system clocks f _c by N are obtained. In FIG. 5, two clock signals CC11 are present, which are difficult to be shown in the drawing when the clock signals CC12 to CC15 below are based on the clock signal CC6. Assuming the clock signal CC11 in Fig. 2, the clock signals CCI2 to CC15 are shown. Subsequently, the clock signals CC12 to CC15 output from the logic circuit unit L, that is, the output of the clock generation unit 30 are applied to the PWM output unit 20 and counting of the main counters latched to the latch circuit unit 10. The value CR is applied to the PWM output unit 20 according to the application of the sampling signal SS, and the high level output of the latch circuit unit 10 is applied among the AND gates AD1 to AD10 of the PWM output unit 20. Only the AND gate that is outputted outputs the clock signal that is the output of the clock generator 30. (Only the AND gate whose output of the latch circuit unit 10 becomes high level outputs the clock signal of the clock generator 30 as it is. Then, the outputs of the AND gates AD1 to AD10 are output as the clock signals W1 to W3 as shown in FIG. 7 via the NOA gates NR1 to NR3 (clock signal W3 in the figure). Since the frequency is very low and does not appear on the drawing, it is shown as an imaginary figure.) The clock signal W1 to W3 pass through the NAND gate ND1 to the seventh. As shown in FIG. 7, FIG. 7 shows the clock signals CC6 to CC10 and the clock signal W1 when the counting value applied to the latch circuit unit 10 is "0000010011" (LSB to MSB). ~ W3) and the waveforms of the PWM signal, as shown in FIG. 7, the PWM signal is a signal in which various clock signals output from the clock generator 30 are logically combined according to the output of the latch circuit unit 10. Therefore, the change in pulse width becomes extremely precise, and the frequency also changes precisely.

In addition, since the clock signals CC6 to CC15 output from the clock generator 30 are the signals passing through the logic circuit unit L (see FIG. 4), the clock signals CC6 to CC15 are inputted to the logical combination. The output signal PWM of the PWM output unit 20 to be output later becomes a high frequency signal.

In summary, the counting value CR of the main counter (not shown) is applied to the latch circuit unit 10 and latched, and the system clock is divided by the clock generator 30 to output the PWM signal as the clock signals CC6 to CC15. 20). At this time, when the counting value CR of the main counter latched according to the sampling signal SS which is the input signal of the latch circuit unit 10 is applied to the PWM output unit 20, the PWM signal is output from the PWM output unit 20. The PWM signal is a logic combination of several clock signals (CC6 ~ CC15) output from the clock generator 30, the frequency and pulse width is changed very precisely, the system clock (f _c ) is a clock generator Since the frequency is divided by passing through the counter C and the logic circuit portion L of 30, the frequency of the clock output from the clock generator 30 can be increased, and a high frequency PWM signal can be obtained.

The present invention which operates as described above can use the clock generator instead of the ripple counter to make the pulse width change and the frequency change of the PWM signal very precise, and can greatly improve the error correction accuracy of the entire servo system. As the frequency of the signal is increased, the PWM signal has a very fast response time to the system clock.

Claims (1)

In a PWM signal generation circuit having a latch circuit section 10 for latching a counting value CR output from a main counter, a counter section for generating clock signals of various frequencies by inputting the system clock f _c ( A clock generator 30 composed of C) and a logic circuit portion L; PWM signal output section 20 composed of a logic circuit (LC) for outputting a PWM signal by inputting the clock signal (CC6 ~ CC15) of the N-bit output of the latch circuit section 10 and the output of the clock generator 30; Frequency variable PWM signal generation circuit composed of

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