KR920003475Y1 - Programmable clock-delay circuit - Google Patents

Abstract

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Description

Programmable Clock Division Circuit

1 is a clock division selecting circuit diagram according to the present invention.

2 is an operating waveform diagram according to the frequency division selection of FIG.

* Explanation of symbols for main parts of the drawings

FF1, FF2, FF3: flip-flop AND1-AND5: AND gate

NOR1-NOR2: Noah gate OR1-OR3: Oagate

NOT1: inverter

The present invention relates to a clock source divider circuit of a digital system, and more particularly, to a circuit for generating a desired clock source by programmatically dividing a main clock according to a predetermined selection action. In general, a system using a microprocessor (Central Processor Unit) (MPU: CPU) or the like uses a clock as an operating source of the MPU. The operation speed of the MPU greatly depends on the clock frequency, and in case of an MPU having 16-bit processing capability, a clock source is used within 8 MHz-12 MHz.

Currently, the most commonly used clock frequency of 286PC AT, a 16-bit personal computer, is 12MHz and 8MHz, and the operating speed is controlled by selecting it using a keyboard key or an external key.

For example, a high speed clock is required to operate the system at high speed, and a low speed clock is required to convert the speed to a low speed.

As described above, the conventional clock generation circuit for supplying the clocks required for the high speed operation mode and the low speed operation mode requires two oscillators, and a circuit such as a separate clock selector is required.

Therefore, the circuit is complicated and has been a factor of the cost increase.

Accordingly, an object of the present invention is to generate a high speed clock and a low speed clock by dividing a clock source oscillating from one oscillator into two, three, or four divisions according to the speed mode selection in a system having more than one speed mode. It is to provide a frequency division selection circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a clock division select circuit according to the present invention, and includes a first flip-flop FF1 for latch delay output of a predetermined state of a logic input by a main clock CLK, and a first flip-flop FF1. A second flip-flop FF2 that latches an output by latching the output by the main clock CLK, and outputs a gate of the second flip-flop FF2 and a first division select logic SELE A no-gate NOR1 outputting an AND gate AND1, an output of the AND gate AND1, and an output of the first flip-flop FF1 to negative logic, and an output and a first output of the first flip-flop FF1. An AND gate AND3 for AND-gating two division select logics SEL1, and an OR gate NOR2 that is enabled according to the state of the second division select logic SEL1 and outputs the inverted gate of the clock CLK. And OR of the outputs of the AND gate AND3 and the NOA gate NOR2 to output the second clock. An inverter NOT1 for inverting and outputting the OR gate OR2, the second division select logic SEL1, and a latch delay output of a logic of a predetermined level by the output clock of the OR gate OP2. The third flip-flop FF3, the output Q of the third flip-flop FF3, and the second division select logic SEL1 are inputted according to the input logic of the second division select logic SEL1. An AND gate AND5 gating the output of the flip-flop FF3, an AND gate AND4 enabled by the output of the inverter NOT1, and gating the output of the first flip-flop FF1; An OR gate OR1 for logically combining the two outputs of the AND gates AND4 and AND5 to the delay input terminal D of the third flip-flop FF3, and the outputs of the OR gate OR1. An AND gate AND2 for performing AND operation on the first division selection logic SEL0, and an output and a third flip of the AND gate AND2. It consists of Iowa gate (OR3) for outputting the output of the drop (FF3) OR.

At this time, the inverter NOT1, the AND gates AND4, AND5, and the OR gate OR1 are the delay input converter 10 for converting the delay input of the third flip-flop FF3, and the AND gate AND3, The NOA gate NOR2 and the OR gate OR2 are clock selectors 20 for converting the input clock of the third flip-flop FF3.

FIG. 2 is an operation waveform diagram of FIG. 1, and FIG. 2A shows that the first and second division selection logics SEL0 and SEL1 output two divisions of the main clock when inputted by two division selection logic.

FIG. 2B shows that the first and second division selection logics SEL0 and SEL1 divide the main clock into three divisions when the three division selection logics are input.

FIG. 3B shows that the first and second division selection logics SEL0 and SEL1 divide the main clock into four divisions when the quadrature selection logic is input.

An operation example of FIG. 1 according to the present invention will now be described with reference to the operation waveform diagram of FIG. 2.

Now, in the circuit of FIG. 1, when the first and second division select signals SEL0 and SEL1 are input "low" as shown in FIG. 2a, and the main clock CLK (about 24 MHz) is input as shown in FIG. The operation of FIG. 1 operates by dividing the main clock CLK by two.

Since the first first division select signal SEL0 is "low", the AND gate AND1 is always "low", and the NOA gate NOR1 is the initial output "low" of the first flip-flop FF1 and the AND. A negative logic output of the output of the gate AND1 outputs "high" as shown in FIG. 2a.

At this time, the first flip-flop FF1 clocks and outputs the negative logic output of the NOA gate NOR1 at the moment when the logic of the main clock CLK becomes the rising edge, thereby outputting a two-divided signal as shown in FIG.

As soon as the output of the first flip-flop FF1 changes to "high", the output of the no-gate NOR1 transitions to "low" in FIG. 2a.

On the other hand, the AND gate AND3 for inputting the output of the first flip-flop FF1 for outputting "high" as shown in FIG. 2A is disabled by the second division select logic SEL1 that is "low" logic and is "low". And the AND gate AND4 inputs the output "high" of the inverter NOT1 to gate the output of the first flip-flop FF1 to the oragate OR1 as it is.

On the other hand, the NOA gate NOR2 for inputting the second division selection logic SEL1 and the main clock CLK in the "low" state is enabled by the second division selection logic SEL1 and input to the main clock CLK. Inverting is input to the clock terminal of the third flip-flop (FF3) through the ora gate (OR2).

At this time, the third flip-flop FF3 inverts the two-divided output of the first flip-flop FF1 input through the AND gate AND4 and the OR gate OR1 to the NOA gate NOR2, thereby causing the OR gate OR2. Clocked by the clock input through the output to the output terminal (Q3) as shown in Figure 2a. The output of the third flip-flop FF3 is output through the oragate OR3.

Therefore, the clock CLKOUT output through the OR gate OR3 is delayed by the T / 2 of the main clock CLK by the NOA gate NOR2.

In addition, the second flip-flop FF2 outputs a clocked delay by the main clock CLK to which the output of the first flip-flop FF1 is input, but this is caused by the first division select signal SEL0 of "low". It is ignored because it is blocked by the gate AND1.

However, if the first and second division select signals SEL0 and SEL1 are both "low", the main clock CLK is divided by the first flip-flop FF1 and divided by the third flip-flop FF3. It can be seen that the output is delayed by the empty period T / 2 of the period T of the clock CLK.

At this time, the frequency of the clock output CLKOUT is a high speed clock.

On the other hand, when the main clock CLK is input while the first and second division select signals SEL0 and SEL1 are "high" and "low", the operation mode of FIG. 1 is operated in three divisions so that the output clock CLKOUT is operated. Outputs a low-speed clock of 8MHz. This operation is as follows.

Now, when the first and second division select signals SEL0 and SEL1 are "high" and "low", and the main clock CLK (24 MHz) is inputted, the NOA gate NOR1 is in two-division operation. As shown in FIG. 2B, the first flip-flop FF1 clocks the output of the NOR gate NOR1 and latches the output of the NOR1 to the output terminal Q1. This is input to the second flip-flop FF2 and the AND gates AND3 and AND4 as described above.

At this time, the second flip-flop FF2 clocks the logic high input signal as shown in FIG. 2b by the input main clock CLK, latches it as shown in FIG. 2b, and delays the output signal to the output terminal Q2.

Therefore, the output of the second flip-flop FF2 is gated by the AND gate AND1 and input to one input terminal of the NOA gate NOR1. That is, in the third division mode, the output of the AND gate G1 becomes the same as the output of the second flip-flop FF2.

On the other hand, the NOA gate NOR1 inputs the "low" and "high" signals, so that its output is converted into "low" as shown in FIG. 2B, and thus the output of the first flip-flop FF1 is also "low". .

As described above, when the first and second frequency division selection signals SEL0 and SEL1 are input to "low, high", the AND gate AND4 outputs two divisions of the first flip-flop FF1 as described above. The gate is input to the OR gate OR1 and the NO gate NOR2 inverts and outputs the main clock CLK.

Therefore, the third flip flop FF3 is output as shown in FIG. 2b in the same manner as in FIG. 2a.

At this time, the AND gate AND2, which inputs the first division selection logic SEL0 "high" to one side, gates the output of the OR gate OR1 and outputs the output as shown in FIG. 2B.

Accordingly, the third division clock as shown in FIG. 2b is output by ORing the OR of the delayed output of the third flip-flop FF3 and the output of the AND gate AND2 from the OR gate OR3.

On the other hand, when the first and second division selection logics SEL0 and SEL1 become " low-high " as shown in FIG. 2C, the AND gate AND1, the no-gate NOR1, the first and second flip-flop FF1 ) And (FF2) are operated in the same manner as in the above-described second division mode. At this time, the output Q1 of the first flip-flop FF1 is shown in FIG. 2C.

On the other hand, the NOA gate NOR, which inputs the main clock CLK to one side, blocks the main clock CLK, which is disabled by the second division select logic SEL1 in the "high" state, and the AND gate ( AND3) provides the output of the first flip-flop FF1 to the clock of the third flip-flop FF3 by the second division select logic SEL1 that is high.

In the state where the AND gate AND3 gates the output of the first flip-flop FF1 as described above, the AND gate AND4 is disabled to output “low”. And AND gate AND5 has an output terminal (3) of third flip-flop FF3 as shown in FIG. ) And the second division selection logic SEL1 in the "high" state are ANDed to output a "high" signal as shown in FIG. 2C.

Therefore, the third flip-flop FF3 outputs the input clock by two divisions. At this time, the input clock of the third flip flop FF3 is a signal divided by two from the first flip flop FF1.

Therefore, according to the input state of the first and second division selection logics SEL0 and SEL1, the operation of FIG. 1 is represented by a truth table as follows.

[Truth table]

As described above, the present invention configures a simple logic gate into a frequency division selection circuit and a frequency division circuit to divide one clock source source into two, three, and four divisions by inputting a division selection signal, as well as a three speed waveform as well as a dual speed CPU speed selection circuit. There is an advantage that can be widely used in a circuit requiring a.

Claims (1)

In a programmable clock division circuit for programmatically dividing one clock source by a division selection signal having a predetermined logic, a first flip-flop for latch delay output of a logic state in a predetermined state by a main clock CLK. (FF1), a second flip flop (FF2) for clocking the output of the first flip flop (FF1) by the main clock (CLKIN), and a latch delay output, and an output of the second flip flop (FF2). An AND gate AND1 for inputting and gating a first division selection logic SEL0, an output of the AND gate AND1, and an output of the first flip-flop FF1 are negatively mixed to perform the first flip-flop ( Noah gate NOR1 outputting to the input terminal of FF1, the outputs of the main clock CLK and the first flip-flop FF1, and two inputs according to the input logic of the second division selection logic SEL1. A gate that only gates one signal to output as a clock A third flip-flop FF3 latch-outputted by the clock conversion circuit 20, the clock of the clock conversion circuit 20, the output of the first flip-flop FF1, and the third flip-flop FF3. The output of the first flip-flop FF1 or the third flip-flop FF3 is gated and selected according to the input logic of the second division select logic SEL1. A periodic conversion circuit 10 provided as an input, an AND gate AND2 for outputting the OR of the output of the periodic conversion circuit 10 and the first division select logic SEL0, and an output of the AND gate AND2; And an OR gate (OR3) for ORing and outputting the output of the third flip-flop (FF3).