KR920003420A - Apparatus and method for damaging the back side of a silicon wafer - Google Patents

Apparatus and method for damaging the back side of a silicon wafer Download PDF

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Publication number
KR920003420A
KR920003420A KR1019900010458A KR900010458A KR920003420A KR 920003420 A KR920003420 A KR 920003420A KR 1019900010458 A KR1019900010458 A KR 1019900010458A KR 900010458 A KR900010458 A KR 900010458A KR 920003420 A KR920003420 A KR 920003420A
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KR
South Korea
Prior art keywords
semiconductor wafer
wafer
fixture
side pieces
silicon carbide
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KR1019900010458A
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Korean (ko)
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KR0180901B1 (en
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로빈슨 존
엘. 보스톤 리키
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엔. 라이스 머레트
텍사스 인스트루먼츠 인코포레이티드
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Publication of KR920003420A publication Critical patent/KR920003420A/en
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Publication of KR0180901B1 publication Critical patent/KR0180901B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

내용 없음No content

Description

실리콘 웨이퍼의 배면측을 손상시키는 장치 및 방법Apparatus and method for damaging the back side of a silicon wafer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 사용된 장치를 도시한 도면,1 shows a device used in the present invention,

제2도는 본 발명에 사용된 반도체 캐리어 고정구를 도시한 도면,2 shows a semiconductor carrier fixture used in the present invention;

제3도는 제2도의 캐리어 고정구의 등각도.3 is an isometric view of the carrier fixture of FIG.

Claims (18)

반도체 웨이퍼의 배면측을 손상시키는 방법에 있어서, 반도체 웨이퍼를 연마 파우더내에 부분적으로 침지시키는 단계, 및 반도체 웨이퍼의 배면측 손상을 발생시키기 위하여 연마 파우더를 진동시키는 단계를 포함하는 것을 특징으로 하는 방법.A method of damaging the back side of a semiconductor wafer, the method comprising partially immersing the semiconductor wafer in abrasive powder, and vibrating the abrasive powder to generate back side damage of the semiconductor wafer. 제1항에 있어서, 연마 파우더가 알루미늄 산화물, 실리콘, 이산화물, 다이아몬드, 붕소 카바이드, 및 실리콘 카바이드를 포함하는 일단의 연마제로 부터 선택되는 것을 특징으로 하는 방법.The method of claim 1 wherein the abrasive powder is selected from a group of abrasives comprising aluminum oxide, silicon, dioxide, diamond, boron carbide, and silicon carbide. 제1항에 있어서, 연마 파우더를 진동시키는 동안 반도체 웨이퍼를 이동하는 단계를 포함하는 것을 특징으로 하는 방법.The method of claim 1 including moving the semiconductor wafer while vibrating the abrasive powder. 제2항에 있어서, 실리콘 카바이드의 입자 크기가 5내지 500미크론인 것을 특징으로 하는 방법.The method of claim 2 wherein the silicon carbide has a particle size of 5 to 500 microns. 제1항에 있어서, 웨이퍼가 진동 연마 파우더에서 회전되는 것을 특징으로 하는 방법.The method of claim 1 wherein the wafer is rotated in vibratory polishing powder. 제1항에 있어서, 반도체 웨이퍼가 웨이퍼 카세트내에 있는 동안 연마되는 것을 특징으로 하는 방법.The method of claim 1 wherein the semiconductor wafer is polished while in the wafer cassette. 제1항에 있어서, 반도체 웨이퍼가 이동 벨트에 덮힌 연마제에 존재하는 동안 연마되는 것을 특징으로 하는 방법.The method of claim 1 wherein the semiconductor wafer is polished while in the abrasive covered by the moving belt. 반도체 웨이퍼의 배면측을 소상시키는 방법에 있어서, 고정구-호울더내에 한개 이상의 반도체 웨이퍼를 장착하는 단계, 실리콘 카바이드의 연마 파우더내에 반도체 웨이퍼를 침지시키는 단계, 및 반도체 웨이퍼의 배면측 손상을 발생시키기 위해 실리콘 카바이드를 진동시키는 동안 반도체 웨이퍼를 회전시키는 단계를 포함하는 것을 특징으로 하는 방법.CLAIMS 1. A method of scraping the back side of a semiconductor wafer, comprising: mounting at least one semiconductor wafer in a fixture-holder, immersing the semiconductor wafer in abrasive powder of silicon carbide, and generating back side damage of the semiconductor wafer. Rotating the semiconductor wafer while vibrating the silicon carbide. 제8항에 있어서, 실리콘 카바이드를 진동시키는 동안 반도체 웨이퍼를 회전시키는 단계를 포함하는 것을 특징으로 하는 방법.9. The method of claim 8 including rotating the semiconductor wafer while vibrating silicon carbide. 제8항에 있어서, 실리콘 카바이드의 입자 크기가 125미크론인 것을 특징으로 하는 방법.The method of claim 8, wherein the particle size of the silicon carbide is 125 microns. 제8항에 있어서, 웨이퍼가 진동 실리콘 카바이드 파우더내에서 약 1분동안 연마되는 것을 특징으로 하는 방법.The method of claim 8, wherein the wafer is polished in vibrating silicon carbide powder for about 1 minute. 웨이퍼의 배면측을 손상시키는 동안 반도체 웨이퍼를 고정시키기 위한 고정구에 있어서, 2개의 측면편, 3개의 맞춤 못 지지대, 및 핸들을 포함하고, 3개의 맞춤 못 지지대가 2개의 측면편에 접속되어 3개의 맞춤 못들간에 반도체 웨이퍼를 지지하고, 핸들이 2개의 측면편에 접속되는 것을 특징으로 하는 고정구.A fixture for holding a semiconductor wafer while damaging the back side of the wafer, the fixture comprising two side pieces, three dowel nail supports, and a handle, wherein three dowel nail supports are connected to two side pieces so that three A fixture for supporting a semiconductor wafer between alignment nails and a handle connected to two side pieces. 제12항에 있어서, 3개의 맞춤 못이, 각각의 맞춤 못이 처리 공정 중에 웨이퍼를 적절하게 고정하기 위해 웨이퍼의 원주상에 반도체 웨이퍼를 접촉시키도록 측면편에 접속되는 것을 특징으로 하는 고정구.13. The fixture of claim 12 wherein three alignment nails are connected to the side pieces such that each alignment nail contacts the semiconductor wafer on the circumference of the wafer to properly secure the wafer during the processing process. 제12항에 있어서, 최소한 한개의 맞춤 못이 반도체 웨이퍼를 장착할 수 있도록 이동시킬 수 있는 것을 특징으로 하는 고정구.13. The fixture of claim 12 wherein at least one dowel nail is movable to mount the semiconductor wafer. 제12항에 있어서, 핸들이 측면편에 회전자재하게 장착되는 것을 특징으로 하는 고정구.The fastener of claim 12 wherein the handle is rotatably mounted to the side piece. 웨이퍼의 배면측을 손상시키는 동안 반도체 웨이퍼를 고정하기 위한 고정구에 있어서, 2개의 측면편, 측면편의 다리들 사이로 연장하는 3개의 고정 못 지지대, 측면편에 회전자재하게 장착된 핸들, 및 2개의 측면편에 접속되어, 3개의 지지못과 2개의 측면편에 접속된 핸들 사이에 반도체 웨이퍼를 지지하는 3개의 고정못 지지대를 포함하고, 각각의 측면편이 중심점으로 부터 동일 지점에 배치되고, 다리가 중심점을 갖고 있는 가상 원주주변의 동일 지점에 배치되는 것을 특징으로 하는 고정구.A fixture for holding a semiconductor wafer while damaging the back side of the wafer, comprising: two side pieces, three fixing nail supports extending between the legs of the side pieces, a handle rotatably mounted to the side pieces, and two side pieces Three nailing pedestals connected to the side and supporting the semiconductor wafer between the three pegs and the handles connected to the two side pieces, each side piece being disposed at the same point from the center point, and the legs being the center point. The fastener, characterized in that arranged at the same point around the virtual circumference. 제16항에 있어서, 3개의 고정못이, 각각의 고정못이 처리 공정 중에 웨이퍼를 적절하게 고정하기 위해 웨이퍼의 원주상에 반도체 웨이퍼를 접촉시키도록 측편에 접속되는 것을 특징으로 하는 고정구.17. The fixture of claim 16 wherein three fixtures are connected to the side pieces such that each fixture contacts the semiconductor wafer on the circumference of the wafer to properly secure the wafer during the processing process. 제17항에 있어서, 최소한 한개의 고정못이 반도체 웨이퍼를 장착할 수 있도록 이동할 수 있는 것을 특징으로 하는 고정구.18. The fixture of claim 17 wherein at least one fixture is movable to mount the semiconductor wafer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010458A 1989-07-12 1990-07-11 Method and apparatus for backside damage of silicon wafers KR0180901B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US378632 1982-05-17
US07/378,632 US5006475A (en) 1989-07-12 1989-07-12 Method for backside damage of silicon wafers

Publications (2)

Publication Number Publication Date
KR920003420A true KR920003420A (en) 1992-02-29
KR0180901B1 KR0180901B1 (en) 1999-04-15

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KR1019900010458A KR0180901B1 (en) 1989-07-12 1990-07-11 Method and apparatus for backside damage of silicon wafers

Country Status (5)

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US (1) US5006475A (en)
EP (1) EP0408341B1 (en)
JP (1) JPH03148828A (en)
KR (1) KR0180901B1 (en)
DE (1) DE69031553T2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2575545B2 (en) * 1990-07-05 1997-01-29 株式会社東芝 Method for manufacturing semiconductor device
JP2719113B2 (en) * 1994-05-24 1998-02-25 信越半導体株式会社 Method for straining single crystal silicon wafer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3923567A (en) * 1974-08-09 1975-12-02 Silicon Materials Inc Method of reclaiming a semiconductor wafer
US4018626A (en) * 1975-09-10 1977-04-19 International Business Machines Corporation Impact sound stressing for semiconductor devices
DE2927220A1 (en) * 1979-07-05 1981-01-15 Wacker Chemitronic METHOD FOR STACK ERROR INDUCING SURFACE DESTRUCTION OF SEMICONDUCTOR DISC
JPH01143223A (en) * 1987-11-28 1989-06-05 Toshiba Corp Surface treatment of semiconductor substrate
FR2631630B1 (en) * 1988-05-18 1990-08-31 Rhone Poulenc Chimie RARE EARTH BASED ABRASIVES

Also Published As

Publication number Publication date
JPH03148828A (en) 1991-06-25
DE69031553D1 (en) 1997-11-13
US5006475A (en) 1991-04-09
KR0180901B1 (en) 1999-04-15
DE69031553T2 (en) 1998-02-12
EP0408341A1 (en) 1991-01-16
EP0408341B1 (en) 1997-10-08

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