KR920003170A - Dual Port Ram Access Control Circuit - Google Patents

Dual Port Ram Access Control Circuit Download PDF

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Publication number
KR920003170A
KR920003170A KR1019900011074A KR900011074A KR920003170A KR 920003170 A KR920003170 A KR 920003170A KR 1019900011074 A KR1019900011074 A KR 1019900011074A KR 900011074 A KR900011074 A KR 900011074A KR 920003170 A KR920003170 A KR 920003170A
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KR
South Korea
Prior art keywords
dual port
port ram
shift register
multiprocessor
signal
Prior art date
Application number
KR1019900011074A
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Korean (ko)
Other versions
KR920004406B1 (en
Inventor
나승혁
최형석
Original Assignee
정용문
삼성전자 주식회사
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Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019900011074A priority Critical patent/KR920004406B1/en
Publication of KR920003170A publication Critical patent/KR920003170A/en
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Publication of KR920004406B1 publication Critical patent/KR920004406B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

내용 없음.No content.

Description

듀얼포트램의 악세스 제어회로Dual Port Ram Access Control Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 종래의 듀얼포트램(dual ported RAM)의 악세스 제어회로를 도시한 구성블록도.1 is a block diagram showing an access control circuit of a conventional dual ported RAM.

제 2 도는 본 발명의 듀얼포트램의 악세스 제어회로를 도시한 구성블록도2 is a block diagram showing an access control circuit of the dual port RAM of the present invention.

제 3 도는 제 2 도에 의한 듀얼포트램의 악세스 제어회로의 일실시예를 도시한 구체회로도.FIG. 3 is a detailed circuit diagram showing an embodiment of an access control circuit of the dual port RAM according to FIG. 2. FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 1', 10 : 시프트레지스터 2, 20 : 제어제지스터1, 1 ', 10: Shift register 2, 20: Control register

3, 3', 30 : 어드레스버퍼부 4, 4', 40 : 데이타버퍼부3, 3 ', 30: address buffer section 4, 4', 40: data buffer section

5, 550 : SRAM 60, 70, 80 : 제 1, 제 2 및 제 3 OR게이트5, 550: SRAM 60, 70, 80: First, second and third OR gates

Claims (3)

멀티프로세서와 듀얼포트램의 사이에서 각 프로세서가 각 포트램을 악세스하기 위하여, 상기 멀티프로세서로부터의 악세스 리퀘스트신호가 아비트레이선회로를 거쳐서 공급되는 래치신호들의 논리합신호에 의해 인에이블되는 시프트레지스터(10)와, 상기 시프트레지스터(10)로 부터의 출력신호와 상기 각각의 래치신호들의 논리합신호들에 의해 인에이블되는 제어레지스터(20)와, 상기 래치신호들만의 논리합신호에 의해 인에이블되는 어드레스버퍼부(30)와; 상기 제어레지스터(20)로부터의 출력신호에 의해 인에이블되는 데이타버퍼부(40)와; 상기 시프트레지스터(10)의 입력단에 설치되어 상기 멀티프로세서로부터의 래치신호들을 논리합하여 상기 시프트레지스터(10) 및 상기 어드레스버퍼수(30)에 인에이블신호를 공급하는 OR게이트(60)와; 상기 시프트 레지스터(10)의 출력단에 설치되어 상기 멀티프로세서로부터의 하나의 래치신호와 상기 시프트레지스터의 하나의 출력신호를 각각 논리합하여 상기 제어레지스터(20)에 인에이블신호를 공급하는 상기 프로세서들 대응하는 수의 게이트들(70,80)을 포함하는 것을 특징으로 하는 듀얼포트램의 악세스 제어회로.In order for each processor to access each port between the multiprocessor and the dual port RAM, a shift register in which the access request signal from the multiprocessor is enabled by the logical sum signal of the latch signals supplied through the abit ray circuit ( 10), the control register 20 enabled by the output signal from the shift register 10 and the logic sum signals of the respective latch signals, and the address enabled by the logic sum signal of only the latch signals. A buffer unit 30; A data buffer unit 40 enabled by an output signal from the control register 20; An OR gate (60) provided at an input terminal of the shift register (10) for supplying an enable signal to the shift register (10) and the address buffer number (30) by ORing the latch signals from the multiprocessor; The processors installed at an output end of the shift register 10 to logically combine one latch signal from the multiprocessor and one output signal of the shift register to supply an enable signal to the control register 20. Access control circuit of a dual port RAM, characterized in that it comprises a number of gates (70, 80). 제 1 항에 있어서, 상기 제어레지스터(20)는 멀티프로세서의 프로세서들의 수에 대응한 수의 서브블록(C1,C2,…Cn)으로 구성됨을 특징으로 하는 듀얼포트램의 악세스 제어회로.The dual port RAM access control circuit according to claim 1, wherein the control register (20) is composed of a number of subblocks (C1, C2, ... Cn) corresponding to the number of processors of the multiprocessor. 제 1 항에 있어서, 상기 듀얼포트램은 SRAM인 것을 특징으로 하는 듀얼포트램의 악세스 제어회로The access control circuit of claim 1, wherein the dual port RAM is an SRAM. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900011074A 1990-07-20 1990-07-20 Dual-port ram accessing control circuit KR920004406B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900011074A KR920004406B1 (en) 1990-07-20 1990-07-20 Dual-port ram accessing control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900011074A KR920004406B1 (en) 1990-07-20 1990-07-20 Dual-port ram accessing control circuit

Publications (2)

Publication Number Publication Date
KR920003170A true KR920003170A (en) 1992-02-29
KR920004406B1 KR920004406B1 (en) 1992-06-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900011074A KR920004406B1 (en) 1990-07-20 1990-07-20 Dual-port ram accessing control circuit

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KR (1) KR920004406B1 (en)

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KR920004406B1 (en) 1992-06-04

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