KR920002517B1 - Method of field effect transistor - Google Patents

Abstract

An insulating layer (4) is selectively deposited on a semi- insulated GaAs substrate (1) on which a buried p type and n+ type layers (3)(8) are formed. The first and second side walls (7)(9) are formed between gate, drain and source and are in contact with the insulating layer (4). An AuGe/Ni layer (11) is formed on the source and drain regions in contact with the n+ type layer (8), while a Ti/Pt/Au gate metal (10) is formed on the gate region. Over the layers an insulating layer (13) and metallic lines (14) are formed in the cited order, and thus, the length of the gate is shortened by providing dual side walls, thereby improving the speed characteristics and reducing noise.

Description

Metal-semiconductor field effect transistor of BPLDD structure by double side wall technology and its manufacturing method

1A to 1F are cross-sectional views showing structures of various types of field effect transistors according to the prior art.

2A to 2F are cross-sectional views illustrating the manufacturing process of the field effect transistor according to the present invention.

* Explanation of symbols for main parts of the drawings

DESCRIPTION OF SYMBOLS 1 Semi-insulation gallium arsenide board | substrate 3: Buried P layer

4, 12, 13: insulating film 5b: temporary gate

7: primary side wall 8: n (+) layer

9: secondary sidewall 10: gate metal

11: AuGe / Ni layer 14: connecting metal wire

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to gallium arsenide (GaAs) metal-semiconductor field effect transistors (MESFETs) for high speed operation. In particular, the present invention relates to fine shape formation and self-alignment using double side wass. BPLDD (Buried P-layer Lightly Doped Drain) Structure by Double Side Wall Technology to Improve Device Characteristics Using Simple Photolithography Technology and High Speed and Low Noise A semiconductor field effect transistor and a method of manufacturing the same.

Currently, the process technology for gallium arsenide digital integrated circuits has been greatly advanced, and 16K SRAM has been announced, and 4K SRAM has been put into practical use. Japan Electric (NEC) and Hitachi (HITACHI), etc. have developed and modified the field-effect transistors (Self-Aligned Implantation for N ⁺ -layer Technology: SAINT) using the outer side wall, similar to the present invention, Japan NTT has also continued to modify and develop self-aligning field effect transistors using dummy gates with a multilayer resist structure.

In addition, TI (Texas Instrument) has developed a unique process technology by improving the self-aligning field effect transistor using the temporary gate of the multilayer resist structure.

In addition, the field effects of T-type gates using gold plating to fabricate high-speed, low-noise field effect transistors used in gallium arsenide digital integrated circuits and monolithic microwave integrated circuits. Transistors, multilayer metal gate type field effect transistors, etc. are being developed, and these field effect transistors are being applied to supercomputers, military communication instruments, and optoelectronic integrated circuits for optical communication.

The field effect transistor, which is an essential element in a gallium arsenide digital integrated circuit, has a source resistance (R _s ) and a source-gate capacitance (C _gs ) to improve the high-speed operation and low noise characteristics of the device. The drain breakdown voltage (V _b ) must be increased to increase the operating range of the device. Therefore, in order to increase the breakdown voltage and reduce the subthreshold current, a field effect transistor having a known BPLDD structure is required.

Referring to the prior art, FIG. 1a is a self-aligning type using an external side wall, and the process is simple, and the effect of reducing the source resistance is reduced. However, since the photolithography technique cannot form a gate of 0.6 microns or less, the cost is high. There was a drawback to use a transfer wire transfer technique, which is very expensive and complicated.

In addition, increasing the n (+) ion implantation energy to increase the K value, which is a characteristic of the current drive, increases the sub-threshold current as a side effect, and damages the surface of gallium arsenide during sidewall etching. As) was flawed to evaporate.

Figure 1b is a self-matching type using a temporary gate that can adjust the gate size to 0.6 microns or less and reduce the resistance of the gate, but it is difficult to remove sidewall etching and oxide film, and complex multilayer resist to form a submicron gate. There was a drawback to using the structure.

In addition, the alignment error generated during gate formation undermines the uniformity of device characteristics, and the capacitance between the source and the gate is large, resulting in noise generated during high frequency operation.

In FIG. 1C, the anisotropic etching of gallium arsenide and the inner sidewall can reduce the size of the gate to 0.6 microns or less, thereby reducing the resistance of the source. However, when reactive ion etching using CF ₄ Cl ₂ damages the surface of gallium arsenide, due to the structure of the gate portion, the capacitance between the source and the gate is large, there is a defect that the noise caused by the current leakage severely.

FIG. 1d is a method of fabricating a self-aligning field effect transistor that can adjust the size of the gate by etching the sidewall of the gate. Since the gate is a T-type, a material having a low specific resistance such as gold (Au) is plated on the upper portion of the gate. Reduce the resistance of the gate.

However, the above method has a defect that is easy to break due to damage to gallium arsenide or unstable etching due to side etching, and gate metal reacts with arsenic arsenide during heat treatment, and the characteristics of the rectification junction are impaired because the arsenide evaporates. There was this.

In FIG. 1e, it is possible to reduce the size of the gate to 0.2 micron very small by iterative deposition, and to increase the breakdown voltage in an asymmetric structure. However, there have been disadvantages in that the direction of the gate must be constant, the reproducibility of the tilt deposition is insufficient, and the gate is asymmetrically formed nonuniformly.

FIG. 1f has the advantage of increasing the breakdown voltage of the drain by increasing the distance between the gate and the drain by forming the sidewalls by the iterative deposition and self-aligning the resistive junction part by the iterative ion implantation.

It is also possible to reduce the operating portion of the gate to 0.6 microns or less by tilting ion implantation. However, the method has a drawback in that current leakage between the drain and the gate is severe due to a defect generated by ion implantation under the gate, and the reproducibility of the tilt deposition and the tilt ion implantation process is insufficient. Therefore, the field effect transistor manufactured by these conventional methods has a problem in that the breakdown voltage is small or difficult to adjust, and the structure and operating range of the device are locally limited.

The present invention overcomes the limitations of photoelectric photoelectric technology to reduce the resistance (R _s ) of the source and the capacitance (C _gs ) of the source-gate in order to solve the conventional problems as described above, self-aligning, drain In order to increase the breakdown voltage and reduce the sub-threshold current, the double side wall technology is used in the BPLDD structure to provide a field effect transistor with a simple device manufacturing process, low noise, and a large operating area. In order to achieve this purpose will be described in detail with reference to the accompanying drawings as follows.

The manufacturing process of the present invention is an insulating film for ion implantation and protecting the surface of the substrate to form an active layer (2) and buried P layer (3) on a semi-insulating gallium arsenide substrate (1) (4) and a first step of depositing an aluminum (Al) film 5a for forming a temporary gate; A second step of forming a temporary gate 5b by photoelectron technique and forming an n (-) layer 6 by ion implantation using the temporary gate 5b to form an LDD structure; In order to form the primary sidewall 7, an insulating layer is deposited and reactive ion etched (RIE), and the n (+) layer 8 is self-aligned to the source and drain portions by ion implantation using the primary sidewall 7. Forming a third process; Depositing and etching the insulating film to form the secondary side wall 9, selectively removing the insulating film 4 to form the gate, and depositing a gate metal 10 of Ti / Pt / Au; A fifth step of depositing and thermally evaporating the insulating film (4) and depositing and thermal evaporation of the AuGe / Ni layer (11) to form a resistive junction between the source and drain, and depositing and etching the insulating film (12) for planarization; In order to form the connection metal line 14, a sixth step of depositing a metal of Ti / Au and then performing pattern formation and ion milling is performed.

In addition, in the field effect transistor of the present invention manufactured by the above process, the insulating film 4 is selectively deposited on the semi-insulated gallium arsenide substrate 1 on which the n (+) layer 8 and the buried P layer 3 are formed. The AuGe / Ni layer 11 is formed in the source and drain portions in contact with the n (+) layer 8, and the gate metal 10 of Ti / Pt / Au is formed in the gate portion. Between the gate, the source and the drain, the primary side wall 7 and the secondary side wall 9 are formed in contact with the insulating film 4, and the insulating film 13 and the connection metal line 14 are sequentially formed thereon. .

Referring to the embodiment of the present invention as described above, in FIG. 2a, a mask during ion implantation to form the active layer 2 of the E / D (Enhancement / Depletion) type field effect transistor on the semi-insulating gallium arsenide substrate 1 The photoresist to be used as a mask is defined to define a place to make an active layer, and the silicon ion (Si ⁺ ) or selenium (Se) depending on the E-FET or D-FET to be made of the active layer 2 using the photoresist as a mask. Ion implantation. The photoresist may be removed by etching with known plasma technology (oxygenplasma) or by acetone.

In order to form the buried P layer 3, ions such as beryllium (Be) and magnesium (Mg), which are P-type impurities, are implanted at an energy of 200-400 keV. The insulating film 4 is deposited on the surface of the gallium arsenide to protect the surface of the gallium arsenide from the process of subsequent dry etching and heat treatment.

Next, an aluminum film 5a is deposited at 1.2 times the height of the desired gate.

In Figure 2e, 20% of this gate height is planarized to eliminate the effect that alignment errors can have on the shape of the gate.

In FIG. 2B, the gate is formed into a photoresist of 0.7-0.9 microns using photolithography, and dry etching is performed to form a temporary gate 5b. Using the temporary gate and the photoresist as a mask, the n (-) layer 6 is ion implanted with an energy of about 100 keV to form an LDD structure.

In FIG. 2C, an insulating film necessary for forming the primary side wall is deposited with a mixed gas of argon and oxygen mixed with nitrogen and 3% silane (SiH ₄ ) to a thickness of about 0.2-0.3 microns. The thickness of the primary side wall and the secondary side wall determined by the thickness of the insulating film is inversely proportional to the magnitude of the source's resistance (R _s ) and the breakdown voltage of the drain, respectively. Become a variable.

The primary side wall 7 is formed by etching the insulating film by reactive ion etching using a mixed gas of hydrogen (H ₂ ) and carbon tetrafluoride (CF ₄ ). When the primary side wall 7 is formed as described above, the ion is implanted under the conditions of high energy and ion dose using silicon ions as a mask to form an n (+) layer 8 by self-alignment in the source and drain portions.

In Fig. 2d, the aluminum gate is wet etched with a known technique of aqueous phosphate solution to completely remove the aluminum temporary gate 5b. The secondary side wall insulating film is deposited and the secondary side wall 9 is fabricated by reactive ion etching in the same manner as the primary side wall fabrication. However, the thickness of the secondary side wall not only determines the length (L _g ) of the gate to be actually formed, but also controls the breakdown voltage of the drain and the resistance of the source-gate. The breakdown voltage of the drain is unevenly affected by the gallium arsenide surface treatment process and increases proportionally as the gate-drain spacing increases.

In the structure of the present invention, the gate-drain spacing is controlled by the primary side wall 7 and the secondary side wall 9. At this time, the limit of the thickness of the secondary side wall should be less than half of the length of the aluminum temporary gate (5b) and the size of about 1/3. When the formation of the double side wall is completed, the active layer 2, the source and the drain are heat-treated at a temperature of 800-850 ° C. for 20 to 30 minutes in a mixed gas atmosphere of hydrogen and asyn ₃ (AsH ₃ ), which is a known technique for activating impurities. Activate the silicon impurities where the resistive junction will be. After forming the photoresist film as a mask, the insulating film of the gate portion is removed by reactive ion etching using a mixed gas of CF ₄ and H ₂ to expose the gallium arsenide surface where the gate is to be formed.

At this time, etching is performed with dilute hydrofluoric acid (HF) solution to prevent damage to the gallium arsenide surface. Next, before the gate metal 10 is deposited, the exposed surface of gallium arsenide is briefly etched with ammonia (NH ₄ OH) based etching solution for washing. In order to form the gate metal 10, a photoresist film for lift-off is formed, and then conventional Ti / Pt / Au is deposited thereon to form a gate. At this time, gallium arsenide is kept at a high temperature to remove impurities such as moisture and at the same time activates the movement of metal ions on the contact surface to improve the adhesion between the deposited metal and gallium arsenide.

In Figure 2e, a photoresist for separation by photophotographic transfer is formed for ohmic bonding of the source and drain.

Thereafter, the insulating film where the resistive junction is to be removed is removed by reactive ion etching. The gallium arsenide in the exposed source and drain portions is etched a little on the surface with an ammonia-based chemical solution to completely remove the remaining oxides and impurities.

Thereafter, the AuGe / Ni layer 11 is deposited, removed, and then subjected to a heat treatment for resistive bonding of the source and drain at a temperature of 400-450 ° C. in a nitrogen atmosphere. In order to planarize, an insulating film 12 is deposited and planarized by reactive ion etching using a mixed gas including CF ₄ , C ₂ F _6, and coral. When the gate is exposed, planarization is performed by reactive ion beam etching using CF ₄ in argon. At this time, the angle of the ion beam is appropriately adjusted and the gate height is simultaneously adjusted.

In FIG. 2F, the insulating film 13 for the primary connection metal line is formed to 1-3 microns, and the contact window is formed by photoelectric transfer and reactive ion etching. Ti / Au, which is a first interconnection metal, is deposited, a pattern of the connecting metal line 14 is formed using photoresist, and then ion milled to form a connecting metal line.

At this time, the gallium arsenide wafer is rotated for uniformity of etching, and the temperature is controlled not to exceed 200 ° C. to prevent damage of the photoresist. Ion milling usually uses argon gas and mills using an ion beam of 300-1000 keV energy. The process up to the formation of the connecting metal line 14 is completed by removing the residual photoresist using an isetone solution and an oxygen plasma.

As described above, according to the present invention, a field effect transistor having a gate length of 0.3-0.5 micron can be fabricated by overcoming the limitation of photoelectric transfer technology by a simple process technology using a double side wall and self-alignment. By fabricating the BPLDD structure, the subthreshold current can be reduced.

That is, the gate length can be reduced by the thickness of the double side wall, so that the parasitic capacitance between the active layer and the gate and the resistance of the source-gate can be reduced, the breakdown voltage of the drain can be kept high, and the reproducibility of the threshold voltage can be reduced. To increase. In addition, the field effect transistors manufactured are simpler than the field effect transistors that have been announced so far, and the device characteristics are controlled and improved.The device structure and the process technology make the driving area larger, and the high speed and low noise characteristics are excellent. There is an effect that can be applied to the fabrication of integrated circuits.

Claims (8)

An insulating film 4 is selectively deposited on the semi-insulating gallium arsenide substrate 1 having the buried P-type 3 and the n (+) layer 8 therebetween, and between the gate, the source and the drain, the insulating film 4 and Primary side walls 7 and secondary side walls 9 are formed in contact with each other. In contact with the n (+) layer 8, AuGe / Ni layers 11 are formed at the source and drain portions, and Ti / is formed at the gate portions. The gate metal 10 of Pt / Au is formed, and the insulating film 13 and the connection metal line 14 are formed thereon, and the gate length is reduced by the thickness of the double side wall to improve the high speed and low noise characteristics. A metal-semiconductor field effect transistor having a BPLDD structure using a double side wall technology. The ion implantation method forms an active layer 2 and a buried p-type 3 on the semi-insulating gallium arsenide substrate 1, and deposits an insulating film 4 for protecting the surface and an aluminum film 5a for forming a temporary gate in this order. 1 step; A second step of forming a temporary gate 5b by photolithography and forming an n (-) layer 6 by ion implantation using the temporary gate 5b to form an LDD structure; A third step of forming a primary side wall (7) by depositing and etching an insulating film and forming an n (+) type (8) by self-alignment in the source and drain portions by ion implantation using the primary side wall (7); The temporary gate 5b is removed, the insulating film is deposited and etched to form a secondary sidewall 9, and after the heat treatment for activating impurities, the insulating film 4 of the gate portion is removed and the gate metal 10 of Ti / Pt / Au is removed. A fourth process of depositing to form a gate; A fifth process of removing the insulating film 4 of the source and drain portions, forming and heat-treating the AuGe / Ni layer 11 to form a resistive junction, depositing and etching the insulating film 12 for planarization, and planarizing etching of the gate and; And a sixth step of depositing an insulating film 13 for the primary connection metal line, forming a contact window, and then depositing a metal of Ti / Au, and then forming the connection metal line 14 by pattern formation and ion milling. Method of manufacturing a metal-semiconductor field effect transistor of the BPLDD structure by the double side wall technology. 2. Double side wall technology according to claim 1, characterized in that it has a primary side wall (7) formed by the temporary gate (5b) and a secondary side wall (9) formed by removal of the temporary gate (5b) by wet etching. Metal-semiconductor field effect transistor of BPLDD structure The method of claim 2, wherein the temporary gate 5b is used as a mask for ion implantation for forming the n (-) layer 6, and the primary for ion implantation for forming the n (+) layer 8 is used. A method of manufacturing a metal-semiconductor field effect transistor having a BPLDD structure by using a double side wall technology, wherein the side wall (7) is used as a mask. The method of claim 2, wherein the primary side wall (7) of the third step is a hydrogen and carbon tetrafluoride after the insulating film is deposited to a thickness of 0.2-0.3 microns in a mixed gas atmosphere of argon and oxygen mixed with nitrogen and 3% silane Method for producing a metal-semiconductor field effect transistor of the BPLDD structure by the double-sided wall technology, characterized in that formed by removing by a reactive ion etching using a mixed gas. The secondary side wall (9) of the fourth process is formed in the same way as the primary side wall (7), but the thickness limit should be less than half the length of the temporary gate (5b) and the size of 1/3. A method of manufacturing a metal-semiconductor field effect transistor having a BPLDD structure by a double side wall technology. The insulating film 12 of the fifth step is planarized by reactive ion etching using a mixed gas containing CF ₂ , C ₂ F ₆ and oxygen, and argon and CF ₄ as gas upon exposure to the gate. A method of manufacturing a metal-semiconductor field effect transistor having a BPLDD structure by double sidewall technology, wherein the planarization is performed by using reactive ion beam etching. The method of manufacturing a metal-semiconductor field effect transistor having a BPLDD structure according to claim 2, wherein the planarization and self-matching resistive junction are simultaneously performed by the double side wall and the reactive ion etching.

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