KR910005399B1 - Manufacturing method of self align type gaas fet using double side space wall - Google Patents

Abstract

The self-aligned GaAs FET using double side wall process is manufactured by: depositing the oxide film (105) for outer side wall after forming a dummy gate (104); ion-implantation the n-type impurity after formign outer side wall (106) by dry etching; forming a inner side wall after depositing the oxide film for inner side wall; depositing the gate metal after removing the nitride film (103) of gate region; forming interconnection metal after depositing the oxide film and photoresist (110). The device is useful for high speed operation and has an advantage for reducing the charge capacity of source-gate and the resistance of source.

Description

Fabrication method of self-aligned gallium arsenide FET using double side wall

1 is a manufacturing process diagram of an embodiment of the present invention.

Figure 1a is a cross-sectional view of depositing an oxide film for the outer side wall after forming the temporary gate.

Figure 1b is a cross-sectional view of n ^- ion implantation after forming the outer side wall by dry etching.

Figure 1c is a cross-sectional view after deposition of the oxide film for the inner side wall.

Figure 1d is a cross-sectional view upon activation after forming the inner side wall.

1E is a cross-sectional view of depositing a gate metal after removing the nitride film of the gate portion.

Figure 1f is a cross sectional view before the resistive junction of a source and a drain removed.

Figure 1g is a cross-sectional planarized after depositing the oxide film and coating the photoresist.

Figure 1h is a cross-sectional view completed after forming the connecting metal properties.

2 is a manufacturing process diagram showing another embodiment of the present invention is the same process as Figures 1a to 1e from Figures 2a to 2e,

2f is a cross-sectional planarization after application of the oxide film.

Figure 2g is a cross-sectional view after the formation of the connecting metal wire.

3 is a cross-sectional view of a self-aligning FET using a conventional outer side wall.

4 is a cross-sectional view of a self-aligning FET using a conventional temporary gate.

5 is a cross-sectional view of a FET using a conventional inner side wall.

6 is a cross-sectional view of a self-aligning FET using conventional gate sidewall etching.

7 is a cross-sectional view of a FET using conventional ital deposition.

8 is a cross-sectional view of a FET by conventional tilt deposition and tilt ion implantation.

* Explanation of symbols for main parts of the drawings

101: semi-insulating gallium arsenide wafer 102: active layer of the FET

103: nitride film 104: temporary gate

105: oxide film for the outer side wall 106: outer side wall

107: n ^- ion implantation layer 108: oxide film for the inner side wall

109: inner side wall 110: photoresist

111 gate 112 resistive bonding metal

113: planarization oxide film 114: insulating film

115: connecting metal wire 116: interlayer for detachment

The present invention relates to a method of manufacturing gallium arsenide (GaAs) field effect transistors (hereinafter referred to as FETs), and to high speed operation. In particular, a dummy gate and double side wall technology and a photolithography method are provided. The present invention relates to a method for fabricating a self-aligned gallium arsenide FET using a double sidewall having a gate size of 0.3-0.5 micron. Manufacture of metal semiconductor FETs using gallium arsenide (MESFET) is a self-aligned implant for n ^- layer technology (FET) type (FET). SWAT: Side Wall Assisted Self Aligned Technology), and self-aligning FETs using temporary gates having the structure shown in FIG. 4 have been developed. The FET, an essential element in gallium arsenide digital integrated circuits, must reduce the source resistance (Rs) and source-gate capacitance (Cgs) to improve the device's high-speed operation and low-noise characteristics. The breakdown voltage of Vb should be increased.

In addition, in order to improve the mass production and reproducibility of the device manufacturing, it is necessary to simplify the manufacturing process.

In the conventional self-aligned FET using the temporary gate, a complex multi-layer resist structure must be used for the formation of the submicron gate, and the alignment error in the gate formation results in uniformity of device characteristics. This results in high noise and large capacitance (Cgs) between the source and the gate, causing noise.

In addition, conventional self-aligned FETs using external sidewalls cannot be applied to photolitography in forming gate shapes of 0.3-0.5 microns, which makes it difficult to use expensive electrophotographic transfer techniques. .

The FET fabricated by these conventional methods has a low breakdown voltage or difficult adjustment, which limits the structure and operating range of the device.

Looking at the prior art in detail, Figure 3 is a self-aligning type using a conventional external side wall, the process is simple, and has the effect of reducing the source resistance, but there is a problem that it is difficult to form a gate of 0.6 microns or less with photo-radiation There is a disadvantage in that the surface of the gallium arsenide is damaged during sidewall etching and the arsenide (As) evaporates during activation heat treatment.

4 is a self-aligning type using a conventional temporary gate, the size of the gate can be adjusted to 0.6 microns or less, and the resistance of the gate can be reduced, but sidewall etching and oxide film are difficult to remove, and also the capacitance between the source and the gate is reduced. This cursor causes noise in high frequency operation.

5 shows that the gate size can be reduced to 8.6 microns or less by using anisotropic etching of gallium arsenide and inner sidewalls, thereby reducing the resistance of the source, but gallium during reactive ion etching using CF ₄ Cl ₂ It damages the surface of arsenic, and the capacitance of the source-gate is large due to the structure of the gate part, and the noise is generated by current leakage.

6 is a method of manufacturing a self-aligning FET which can be adjusted to a smaller gate (111a to 111b) by etching sidewalls of the gate. Also, since the gate is T-type, a material having a low resistivity such as Au is used on the upper portion of the gate. Reduce the resistance of the gate.

However, as shown in FIG. 4, the gallium arsenide may be damaged or the etching may be unstable due to unstable etching, and the gate metal 111b and the gallium arsenide may react during heat treatment. As a result of evaporation of arsenide, the characteristics of the rectifying junction may be impaired. do.

FIG. 7 shows that the gate size can be reduced to as small as 0.2 micron with conventional iterative deposition, and the breakdown voltage can be increased with an asymmetric structure, but the direction of the gate must be constant, and the reformation of the italic deposition is insufficient, and the gate Has the disadvantage of being formed asymmetrically and nonuniformly.

FIG. 8 has the advantage of increasing the breakdown voltage of the drain by increasing the distance between the gate and the drain by forming a sidewall with a conventional iterative deposition and self-aligning the resistive junction part by the tilting ion implantation, and tilting the operation portion of the gate. It can be reduced to less than 0.6 micron by using a defect, but due to the defects generated by ion implantation under the gate, the current leakage between the drain and the gate is severe, and there is a disadvantage in that it is insufficient to re-form the tilt deposition and the tilt ion implantation process.

The present invention has been devised to solve the above problems, to overcome the limitation of photo-transfer transfer technology 0.6-0.7 microns to produce a gate size of 0.3-0.5 microns, the gate length (Lg) is small Therefore, the parasitic capacitance between the active layer and the gate is small and the self-matching type makes the source-gate resistance small and the breakdown voltage can be increased and controlled by the thickness of the double side wall. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A is a cross-sectional view of depositing an oxide layer 105 for an external sidewall after forming a temporary gate 104. An active layer of an E / D (Enhancement / Depletion) FET is formed on a semi-insulating gallium arsenide wafer 101. To form the active layer 102 by applying a photoresist to be used as a mask when implanting ions to form the active layer 102 and heat-treating at 100-110 ° C., the E-FET to make the active layer 102 as a mask ion implantation is a requirement of 1X10 ¹³ cm ^-2 - 1X10 ¹² of silicon ion (Si ⁺⁾ 40-150KeV in accordance with the D-FET.

The photoresist is removed by etching with oxygen plasma.

On the other hand, the removal of the photoresist using acetone is cleaned with ultrasonic waves, and the surface of the gallium arsenide 102a is removed from a process such as dry etching and heat treatment by depositing about 600-1000 Å of the nitride film 103 on the surface of gallium arsenide. Protect.

Next, aluminum 104 is deposited to a thickness about 20% larger than the height of the desired date, and later 20% of this gate height is etched to eliminate the effect that alignment errors can have on the shape of the gate.

The gate is formed of photoresist with a photoresist of 0.7-0.9 microns and photo-etched to form a temporary gate 104 by dry etching aluminum with a mixed gas of argon containing a gas of SiCl ₂ and CCl ₂ .

An oxide film 105 for forming the outer sidewalls on the temporary gate 104 is deposited at 300-450 ° C. with a mixed gas of argon and oxygen mixed with nitrogen and 3% SiH ₄ to a thickness of about 0.2-0.3 microns.

In this case, since the thickness of the outer side wall controlled by the thickness of the oxide film 105 has a relationship inversely proportional to the magnitude of the breakdown voltage of the source and the drain, one variable controlling the characteristics of the manufactured FET Becomes

1b is a cross-sectional view of ion-implantation of n ⁻ after the external side wall 106 is formed by dry etching, and the oxide film is etched at an etching rate of 300-700 Å / min using a mixed gas of H ₂ and CF ₄ at an input of about 200 mTorr. After the side wall 106 is formed, silicon ions are implanted under the conditions of high energy and high ion amount using the outer side wall 106 as a mask to form an n ⁻ layer on the source 107a and drain 107b portions by self-alignment. .

Figure 1c is a cross-sectional view of the oxide film for the inner side wall 108, the aluminum gate is etched for washing with an aqueous solution containing phosphoric acid (H ₃ PO ₄ ) in deionized water and wet etching with a phosphoric acid solution aluminum The temporary gate 104 is completely removed.

FIG. 1D is a cross sectional view of the inner side wall 109 after activation, and the inner side wall 109 is manufactured by oxide film deposition and reactive ion etching in the same manner as the outer side wall 106 of FIG. 1B.

In this case, the thickness Low of the inner side wall 109 becomes a variable that determines the length Lg of the gate to be actually formed, thereby controlling the breakdown voltage of the source-gate resistance and the drain.

The breakdown voltage of the drain is unevenly influenced by the surface treatment of gallium arsenide, and increases slightly as the gate-drain spacing increases.

In the structure of the present invention, the gate-drain spacing is controlled by the inner side 109 and the outer side wall 106.

At this time, the limit of the thickness of the inner side wall 109 should be less than half of the length of the aluminum temporary gate, and should be about 1/3 of the length of the temporary gate in consideration of the difficulty of deposition and sidewall etching.

After the formation of the double side wall is completed for 20 minutes to 30 minutes heat treatment at a temperature of 800-850 ℃ in a mixed gas atmosphere of hydrogen and asin (AsH ₃ ) to activate the impurities resistive bonding of the active layer 102 and the source and drain The silicon impurity of the n ⁻ ion implantation layer 107 will be activated.

FIG. 1E is a cross-sectional view of depositing the gate metal 111 after removing the nitride film of the gate portion. When the 0.3-0.5 micron gate 111 portion is formed by the process of FIG. 1D, the gate is formed using the photoresist film 110 as a mask. The negative nitride film is removed by reactive ion etching using a mixed gas of CF ₄ and H ₂ to expose the gallium arsenide surface 102a where the gate is to be formed, in order to prevent damage to the gallium arsenide surface 102a. The final 100 Å is wet etched with dilute hydrofluoric acid (HF) solution.

Next, before the gate metal 111 is deposited, the exposed gallium arsenide surface 102a is briefly etched with ammonia (NH ₄ OH) based etching solution for washing.

In order to form the gate metal 111, a photoresist film 110 for detachment is formed, and Ti / Pt / Au is deposited thereon to a thickness of about 1000/1000/3000 mm3.

At this time, gallium arsenide is kept at a high temperature to remove impurities such as moisture and at the same time activates the movement of metal ions at the contact surface to improve adhesion between the deposited metal and gallium arsenide, and then the same oxygen plasma and acetone as in FIG. 1a. Cleaning is used to remove the photoresist 110.

FIG. 1F is a cross-sectional view of the resistive bonding metal 112 of the source and drain, before forming the photoresist 110 for photoresist transfer for resistive bonding of the source and drain, and then forming a resistive junction. The nitride film 103 is removed by reactive ion etching in the same manner as in FIG. 1A.

The gallium arsenide in the exposed source and drain portions is slightly etched with an ammonia-based chemical solution to completely remove residual oxides and impurities, and then the resistive bonding metal 112 composed of AuGe / Ni to a thickness of about 800 / 200Å. After deposition, the photoresist 110 is removed (Lift-off), heat treatment for resistive bonding of the source and drain is performed at 400-450 ° C. in a nitrogen atmosphere.

Figure 1g is a cross-sectional planarization after oxide film deposition and photoresist coating to deposit a planarization oxide film 113 of about 0.8 microns for planarization and reactive ion etching using a mixed gas containing CF ₄ , C ₂ F ₅ and oxygen Flatten.

When the gate is exposed by such a planarization operation, a reactive ion beam etching using CF ₄ is used for argon. At this time, by adjusting the angle of the ion beam, 20% of the gate is etched to adjust the desired gate height at the same time.

FIG. 1h is a cross-sectional view formed after forming the connection metal line by ion milling, forming an contact phase by depositing an insulating film 114 for 1-3 microns on the oxide film 113, and depositing an interconnection metal. After forming the photoresist as a mask, ion milling is performed to form the connection metal wire 115.

At this time, the gallium arsenide wafer 101 is rotated for uniformity of etching, and the temperature is controlled not to exceed 200 ° C. to prevent damage to the photoresist, and the ion milling uses argon gas at a pressure of ² × 10 ⁻⁴ torr. Milling using an argon ion beam.

Subsequently, the residual photoresist is removed using an acetone solution and an oxygen plasma to complete the process up to the connecting metal line 115.

On the other hand, in another embodiment of the double side wall, the FET can be fabricated by forming the self-matching rectifier junction in the same manner as in FIG.

In other embodiments, the same procedure is performed from FIGS. 1A to 1E and the self-aligning process for resistive bonding between the source and the drain is performed from FIG. 2F.

FIG. 2F is a planarization cross-sectional view after application of the oxide film 113 to define an active layer portion of the FET including the gate portion for resistive bonding with a photoresist, remove the nitride film, and then deposit and remove the resistive metal 112, and then deposit an oxide film thereon. 113 is deposited and planarized to reactive ion etching as shown in FIG. 1C, and the portions of source 112a and drain 112b of source 112a of resistive metal 112 are disconnected by reactive ion etching.

At this time, the gate is etched by about 20% to planarize the height of the gate, and the resistive metal 112 is reliably separated.

In this manner, when the planarization is performed, the oxide film 113 is deposited to form a connection metal line in the same manner as in FIG. 1h to complete a FET having a structure as illustrated in FIG. 2g.

As described above, the present invention can form a gate size of 0.3-0.5 micron using double sidewalls, so that the resistance of the source and the source-gate capacitance are reduced, and the breakdown voltage of the drain is properly adjusted. In addition, the process technology of self-aligning by double side walls is simpler than conventional manufacturing methods, and thus, the reproducibility is increased.

Claims (11)

In the method of manufacturing a fast-acting gallium arsenide FET, after forming the temporary gate 104, an oxide film 105 for the outer side wall is deposited, and after forming the outer side wall 106 by dry etching, n ⁻ is ion implanted, and then the inside After depositing the sidewall oxide film 108, the inner side wall 109 is formed and activated. Then, the nitride film 103 of the gate 111 is removed, and then the gate metal is deposited to remove the resist from the source and drain. After the bet, the oxide film is deposited and the photoresist 110 is applied and planarized, and the connection metal line 115 is formed and completed to reduce the resistance of the source and the capacitance of the source-gate by using long-term matching with the double side wall. A method of manufacturing a self-matching gallium arsenide FET using a double side wall, characterized in that to control the breakdown voltage of the drain at the same time. The method of claim 1, wherein the temporary gate 104 is formed by photolithography to form a 0.7-0.9 micron photoresist and dry etching aluminum with a mixture of argon containing a gas of SiCl ₄ and CCl ₂ A method of manufacturing a self-aligning gallium arsenide FET using a double side wall. The deposition of the oxide film 105 for the outer side wall is performed by argon with a mixture of nitrogen and 3% SiH ₄ in a thickness of 0.2-0.3 micron in the thickness of the oxide film 105 necessary for the formation of the outer side wall on the temporary gate 104. A method of manufacturing a self-aligning gallium arsenide FET using a double side wall, which is deposited by a mixed gas of oxygen. The method of claim 1, wherein the outer side wall 106 is formed by etching an oxide layer using a reactive ion etch using a mixed gas of H ₂ and CF ₄ . . The method of claim 1, wherein the n ⁻ ion implantation is performed by self-aligning the source 107a and the drain 107b by implanting silicon ions under the condition of high energy and high ion amount using the outer side wall 106 as a mask. A method of manufacturing a self-aligning gallium arsenide FET using a double side wall. The method of manufacturing a self-aligning gallium arsenide FET using a double side wall according to claim 1, wherein the deposition of the inner side wall oxide film 108 is performed by wet etching the aluminum temporary gate 106 with a phosphate solution. . The method of manufacturing a self-aligning gallium arsenide FET using a double side wall according to claim 1, wherein the inner side wall (109) is formed by oxide film deposition and reactive ion etching. 8. The magnet using the double side wall according to claim 1, wherein the gate-drain spacing is controlled by the inner side wall 109 and the outer side wall 106. Method of manufacturing a matched gallium arsenide FET. 2. The self-aligning method of claim 1, wherein the planarization operation is performed by depositing an oxide layer 113 for planarization and planarization by reactive ion etching using a mixed gas containing oxygen of CF ₄ and C ₂ F ₅ . Method for producing a gallium arsenide FET. The method of claim 1, wherein the forming of the connecting metal wire 15 by ion milling comprises forming a contact field with an insulating film, depositing the connecting metal wire 115, and ion-milling using a photoresist as a mask. A method of manufacturing a self-aligning gallium arsenide FET using a double side wall. 10. The planarization operation according to claim 1 or 9, wherein the planarization operation defines the active layer portion of the FET including the gate portion for the resistive junction as photoresist 110, and after the deposition of the resistive metal 112 is removed with a mask. A method of manufacturing a self-aligning gallium arsenide FET using a double side wall, characterized in that the oxide film 113 is deposited thereon and planarized by reactive ion etching.

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