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Application filed by 문정환, 금성일렉트론 주식회사filedCritical문정환
Priority to KR1019900008485ApriorityCriticalpatent/KR920001637A/en
Publication of KR920001637ApublicationCriticalpatent/KR920001637A/en
Insulated Gate Type Field-Effect Transistor
(AREA)
Formation Of Insulating Films
(AREA)
Abstract
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Description
LDD 스페이서 제조방법LDD spacer manufacturing method
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도 본 발명 LDD 스페이서 제조공정을 나탄낸 단면도.2 is a cross-sectional view showing the LDD spacer manufacturing process of the present invention.
Claims (2)
기판(1)위에 게이트(2)을 형성한 후 이에 CVD 산화막(3)을 디포지션하고 상기 게이트(2) 상방으 CVD산화막(3)위에 포토리지스트(4)를 형성한 후 이방성 RIE 공정으로 예치하여 수직 LDD 스페이서(3 b)를 형성하고 이어 포토리지스트(4)를 제거함을 특징으로 하는 LDD스페이서 제조방법.After the gate 2 is formed on the substrate 1, the CVD oxide film 3 is deposited thereon, the photoresist 4 is formed on the CVD oxide film 3 above the gate 2, and then subjected to an anisotropic RIE process. Depositing to form a vertical LDD spacer (3b) and then removing the photoresist (4).제1항에 있어서, 포토리지스트(4)의 선폭으로 LDD스페이서(3 b)의 길이를 조정함을 특징으로 하는 LDD스페이서 제조방법The method of manufacturing an LDD spacer according to claim 1, wherein the length of the LDD spacer 3b is adjusted to the line width of the photoresist 4.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.