KR920000035A - 인터페이스 시스템 및 데이타 전송 제어방법 - Google Patents

인터페이스 시스템 및 데이타 전송 제어방법 Download PDF

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KR920000035A
KR920000035A KR1019910001522A KR910001522A KR920000035A KR 920000035 A KR920000035 A KR 920000035A KR 1019910001522 A KR1019910001522 A KR 1019910001522A KR 910001522 A KR910001522 A KR 910001522A KR 920000035 A KR920000035 A KR 920000035A
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task
scheduled
entry
executed
interface system
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KR1019910001522A
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KR950002713B1 (ko
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트루만 앳킨즈 죤
스탠리 포거젤스키 제임스
헤지더스 윌슨 재크린
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하워드 지.피거로아
인터내셔널 비지네스 머신즈 코포레이션
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음.

Description

인터페이스 시스템 및 데이타 전송 제어방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 호스트 컴퓨터 시스템의 블럭선도.
제2도는 제1도의 시스템과 함께 사용하기 위한 양호한 직렬 통신 어댑터의 블럭선도.
제3도는 본 발명에 따른 양호한 스케쥴러 작업 테이블을 도시한 도면.

Claims (14)

  1. 다수의 통신단자와 호스트 시스템 간의 데이타 전송을 제어하기 위한 방법으로서, 단자와 중간 메모리 간의 데이타 전송 및 중간 메모리와 호스트 시스템간의 데이타 전송을 실시하기 위한 다수의 타스크를 규정하는 단계와, 규정된 타스크에 우선순위를 지정하는 단계와, 단자에서의 호스트 시스템 내에서 발생하는 이벤트에 응답하여 실행되는 타스크를 스케쥴링하는 단계와, 타스크가 완결될 때, 모든 스케쥴된 타스크중 가장 높은 우선순위를 가진 다음번에 실행될 타스크를 선택하는 단계를 구비하는 데이타 전송 제어방법.
  2. 제1항에 있어서, 타스크는 라운드 로빈 방식을 사용하여 스케쥴된 모든 단자에 대해 실행되는 데이타 전송 제어방법.
  3. 제1항에 있어서, 상기 스케쥴링 단계는, 규정된 타스크 각각에 대해 엔트리를 가진 테이블을 제공하는 단계를 포함하며, 여기서 타스크는 대응 테이블 엔트리에 정보를 기입하여 스케쥴되는 데이타 전송 제어방법.
  4. 제3항에 있어서, 테이블내의 적어도 한 엔트리는 단자들 중 하나에 각각 대응하는 다수의 서브엔트리를 가지며, 타스크는 대응 서브 엔트리에 정보를 기입함으로서 단자에 대해 실행되도록 스케쥴되는 데이타 전송 제어방법.
  5. 제4항에 있어서, 각각의 버스 엔트리는 1 데이타 비트를 포함하는 데이타 전송 제어방법.
  6. 제3항에 있어서, 테이블 내의 적어도 한 엔트리는 대응 타스크가 스케쥴된 횟수의 카운트를 나타내며, 타스크는 엔트리에서 값을 증가시킴으로써 스케쥴되는 데이타 전송 제어방법.
  7. 제1항에 있어서, 타스크가 스케쥴되게하는 이벤트는 호스트 시스템 또는 단자에 의해 일어나는 하드웨어 인터럽트를 포함하는 데이타 전송 제어방법.
  8. 제8항에 있어서, 타스크가 스케줄되게하는 이벤트의 스케쥴된 타스크의 실행을 더 포함하는 데이타전송 제어방법.
  9. 다수의 통신 단자를 호스트 시스템과 인터페이싱시키는 인터페이스 시스템으로서, 호스트 시스템과의 인터페이스와; 중간 메모리와; 인터페이스 시스템의 동작을 제어하기 위한 처리기와; 다수의 통신 단자와; 상기 호스트 인터페이스, 상기 중간 메모리, 상기 처리기, 상기 통신단자를 연결시키는 버스와; 상기 처리기에 의해 실행되는 다수의 통신 타스크와; 상기 타스크의 실행을 스케쥴하기 위한 수단을 구비하는 인터페이스 시스템 .
  10. 제9항에 있어서, 각각의 통신 타스크에는 우선순위 레벨이 지정되며, 높은 우선순위 레벨을 가진 스케쥴된 타스크는 낮은 우선순위 레벨을 가진 스케쥴된 타스크 보다 먼저 실행되는 인터페이스 시스템.
  11. 제9항에 있어서, 상기 스케쥴링 수단은 상기 타스크에 대응하는 엔트리를 가진 테이블을 포함하며, 타스크는 대응 테이블 엔트리에 정보를 기입함으로서 스케쥴되는 인터페이스 시스템.
  12. 제11항에 있어서, 정보는 호스트 시스템 및 상기 통신단자에 의해 발생된 인터럽트에 응답하여 테이블 엔트리에 기입되는 스케쥴되는 인터페이스 시스템.
  13. 제12항에 있어서, 정보는 또한 타스크를 실행함으로서 데이블 엔트리에 기입되는 스케쥴되는 안터페이스 시스템.
  14. 제11항에 있어서, 적어도 한 엔트리는 상기 통신 단자 중 하나에 각각 대응하는 다수의 비트를 포함하며, 타스크는 그 대응 비트에 기입함으로서 상기 단자 중 하나에 대해 실행되도록 스케쥴되는 인터페이스 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910001522A 1990-02-14 1991-01-30 인터페이스 시스템 및 데이타 전송 제어방법 KR950002713B1 (ko)

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US07/479,777 1990-02-14
US07/479,777 US5247671A (en) 1990-02-14 1990-02-14 Scalable schedules for serial communications controller in data processing systems

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KR920000035A true KR920000035A (ko) 1992-01-10
KR950002713B1 KR950002713B1 (ko) 1995-03-24

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US (1) US5247671A (ko)
EP (1) EP0442615B1 (ko)
JP (1) JPH0727503B2 (ko)
KR (1) KR950002713B1 (ko)
CN (1) CN1021536C (ko)
AU (1) AU649642B2 (ko)
DE (1) DE69130620T2 (ko)
MY (1) MY105323A (ko)
NZ (1) NZ236764A (ko)
SG (1) SG42809A1 (ko)

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US5247671A (en) 1993-09-21
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SG42809A1 (en) 1997-10-17
KR950002713B1 (ko) 1995-03-24
MY105323A (en) 1994-09-30
EP0442615A2 (en) 1991-08-21
DE69130620T2 (de) 1999-07-22
DE69130620D1 (de) 1999-01-28
JPH04215158A (ja) 1992-08-05
AU649642B2 (en) 1994-06-02
AU6935991A (en) 1991-08-15
EP0442615B1 (en) 1998-12-16
CN1054160A (zh) 1991-08-28

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