KR910019099U - 풀 레벨 출력 버퍼회로 - Google Patents

풀 레벨 출력 버퍼회로

Info

Publication number
KR910019099U
KR910019099U KR2019900003959U KR900003959U KR910019099U KR 910019099 U KR910019099 U KR 910019099U KR 2019900003959 U KR2019900003959 U KR 2019900003959U KR 900003959 U KR900003959 U KR 900003959U KR 910019099 U KR910019099 U KR 910019099U
Authority
KR
South Korea
Prior art keywords
output buffer
buffer circuit
level output
full level
full
Prior art date
Application number
KR2019900003959U
Other languages
English (en)
Other versions
KR930003019Y1 (ko
Inventor
심재철
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019900003959U priority Critical patent/KR930003019Y1/ko
Publication of KR910019099U publication Critical patent/KR910019099U/ko
Application granted granted Critical
Publication of KR930003019Y1 publication Critical patent/KR930003019Y1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR2019900003959U 1990-04-02 1990-04-02 풀 레벨 출력 버퍼회로 KR930003019Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900003959U KR930003019Y1 (ko) 1990-04-02 1990-04-02 풀 레벨 출력 버퍼회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900003959U KR930003019Y1 (ko) 1990-04-02 1990-04-02 풀 레벨 출력 버퍼회로

Publications (2)

Publication Number Publication Date
KR910019099U true KR910019099U (ko) 1991-11-29
KR930003019Y1 KR930003019Y1 (ko) 1993-05-27

Family

ID=19297317

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019900003959U KR930003019Y1 (ko) 1990-04-02 1990-04-02 풀 레벨 출력 버퍼회로

Country Status (1)

Country Link
KR (1) KR930003019Y1 (ko)

Also Published As

Publication number Publication date
KR930003019Y1 (ko) 1993-05-27

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Legal Events

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Payment date: 20040326

Year of fee payment: 12

EXPY Expiration of term