KR910015038A - A semiconductor device having a supporting member and a method of manufacturing the semiconductor device - Google Patents

A semiconductor device having a supporting member and a method of manufacturing the semiconductor device Download PDF

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Publication number
KR910015038A
KR910015038A KR1019910000987A KR910000987A KR910015038A KR 910015038 A KR910015038 A KR 910015038A KR 1019910000987 A KR1019910000987 A KR 1019910000987A KR 910000987 A KR910000987 A KR 910000987A KR 910015038 A KR910015038 A KR 910015038A
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South Korea
Prior art keywords
semiconductor device
groove
conductor
semiconductor element
semiconductor
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KR1019910000987A
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Korean (ko)
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KR100198209B1 (en
Inventor
마리아 코르넬리스 페르스베크 요하네스
아드리아누스 루이스 라르호펜 헨리쿠스
빌헬무스 마리아 판데 바테르 피터
판 미덴도르프 얀
보에르 코르넬리스
Original Assignee
프레데릭 얀 스미트
엔. 브이. 필립스 글로아이람펜 파브리켄
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Publication of KR910015038A publication Critical patent/KR910015038A/en
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Publication of KR100198209B1 publication Critical patent/KR100198209B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

내용 없음No content

Description

지지부재를 구비하는 반도체 장치와 그 반도체 장치를 제조하는 방법A semiconductor device having a supporting member and a method of manufacturing the semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 반도체 장치를 도시하는 도면, 제2도는 제1도에 도시된 반도체 장치의 단면도, 제3도는 제1도에 도시된 반도체 장치의 다른 실시예를 도시하는 도면.1 is a diagram showing a semiconductor device according to the present invention, FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1, and FIG. 3 is a view showing another embodiment of the semiconductor device shown in FIG.

Claims (14)

지지부재에 걸쳐 연장하는 전도체가 존재하는 벽을 가지고 있는 홈과, 상기 홈에 제공되어 상기 벽상의 전도체와 전기 접촉을 형성하는 반도체 소자가 제공된 상기 지지부재를 구비하는 반도체 장치에 있어서, 상기 반도체 소자를 홈내에서 클램프함으로써, 상기 벽상의 전도체와 전기적 접촉을 형성시키는 것을 특징으로 하는 반도체 장치.A semiconductor device comprising a groove having a wall with a conductor extending over the support member, and the support member provided with the groove to form a semiconductor element in electrical contact with the conductor on the wall. Is formed in electrical contact with the conductor on the wall by clamping in the groove. 제1항에 있어서, 상기 홈은 하향 방향으로 점차 작아지는 단면의 테이퍼진 형상을 가지며, 상기 홈내에서 상기 반도체 소자가 클램핑 고정되어 자동적으로 보유되는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the groove has a tapered shape of a cross section gradually decreasing in the downward direction, and the semiconductor element is clamped and held automatically in the groove. 제2항에 있어서, 상기 홈의 벽들은 5° 내지 15°의 각도를 이루는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 2, wherein the walls of the grooves are at an angle of 5 ° to 15 °. 선행 항중의 어느 한 항에 있어서, 상기 반도체 소자와 상기 전도체중의 하나의 전도체와의 사이에서 납땜 접속이 제공되는 것을 특징으로 하는 반도체 장치.The semiconductor device according to any one of the preceding claims, wherein a soldered connection is provided between the semiconductor element and one of the conductors. 선행 항중의 어느 한 항에 있어서, 상기 반도체 소자와 상기 전도체중의 하나의 전도체와의 사이에 변형가능한 접점부재가 제공되는 것을 특징으로 하는 반도체 장치.The semiconductor device according to any one of the preceding claims, wherein a deformable contact member is provided between the semiconductor element and one of the conductors. 제5항에 있어서, 상기 변형가능한 접점부재는 와이어 본딩에 의해 상기 반도체 소자상에 제공된 범프 접점인 것을 특징으로 하는 반도체 장치.6. A semiconductor device according to claim 5, wherein said deformable contact member is a bump contact provided on said semiconductor element by wire bonding. 제6항에 있어서, 상기 범프 접점은 금 또는 은으로 이루어진 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 6, wherein the bump contact is made of gold or silver. 지지부재에 걸쳐 연장하는 전도체가 존재하는 벽을 갖는 홈과, 상기 홈내에 제공되어 상기 벽상의 상기 전도체와 전기적 접촉을 형성하는 반도체 소자가 제공된 상기 지지부재를 구비하는 반도체 장치를 제조하는 방법에 있어서, 상기 방법은 상기 전도체가 존재하는 벽을 갖는 연속하여 이어지는 홈이 제공된 지지 봉을 가지고 시작하고, 그 후 반도체 소자를 상기 홈에 제공하여 클램핑 고정하고, 상기 지지 봉을 다수의 반도체 장치로 분할하는 것을 특징으로 하는 방법.A method of manufacturing a semiconductor device, comprising: a groove having a wall with a conductor extending over the support member; and the support member provided with the semiconductor element provided in the groove to form electrical contact with the conductor on the wall. The method starts with a support rod provided with successive successive grooves with walls in which the conductor is present, and then provides a semiconductor element to the groove to clamp and fix the support rod into a plurality of semiconductor devices. Characterized in that the method. 제8항에 있어서, 상기 반도체 소자를 하향 방향으로 점차 작아지는 단면의 테이퍼진 홈내로 밀어넣으므로써 홈내에 제공되어 클램핑 고정되며, 상기 홈내에서 상기 반도체 소자는 자동적으로 클램핑 고정되어 보유되는 것을 특징으로 하는 방법.9. The method of claim 8, wherein the semiconductor device is provided in the groove and clamped by pushing the semiconductor device into a tapered groove of gradually decreasing cross section, wherein the semiconductor device is automatically clamped and held in the groove. How to. 제8항 및 제9항중 어느 한 항에 있어서, 상기 반도체 소자를 홈 내부로 삽입하기 전에 납땜 층을 상기 전도체 또는 상기 반도체 소자에 제공하며, 상기 반도체 소자를 삽입한 후 상기 본도체 소자를 가지고 있는 상기 지지봉을 가열하는 방법.10. The method according to any one of claims 8 and 9, wherein a solder layer is provided to the conductor or the semiconductor element before the semiconductor element is inserted into the groove, and after the semiconductor element is inserted, the main conductor element is provided. Heating the support rod. 제8항, 제9항 또는 제10항에 있어서, 상기 반도체 소자를 상기 홈에 삽입하기 전에 변형 가능한 접점부재를 상기 반도체 소자에 제공하는 것을 특징으로 하는 방법.The method according to claim 8, 9 or 10, characterized in that the deformable contact member is provided to the semiconductor element before inserting the semiconductor element into the groove. 제11항에 있어서, 상기 반도체 소자를 상기 반도체 소자가 반도체 슬라이스상에서 그 형태를 그대로 유지하고 있는 동안, 상기 접점부재를 상기 반도체소자에 제공하며 그후 상기 슬라이스를 상기홈에 삽입되는 개개의 반도체 소자로 분할하는 것을 특징으로 하는 방법.12. The semiconductor device according to claim 11, wherein the semiconductor device is provided to the semiconductor device while the semiconductor device maintains its shape on the semiconductor slice as it is, and then the slice is inserted into the groove. Dividing. 지지 봉에 걸쳐 연장하는 전도체가 존재하는 벽을 가지고 있는 홈이 제공된 상기 지지봉을 제조하는 방법에 있어서, 상기 지지봉을 금속을 이용하여 무전해 결정핵 생성하는 단계와; 상기 금속을 국부적으로 제거하거나 또는 상기 금속을 절연하는 단계와; 나머지 부분의 상기 금속의 두께를 전기화학적으로 두껍게 하는 단계로 상기 전도체를 상기 지지 봉에 제공하는 것을 특징으로 하는 방법.CLAIMS 1. A method of making a support rod provided with a groove having a wall in which a conductor extends across the support rod, the method comprising the steps of: generating electroless crystal nuclei using the metal; Locally removing the metal or insulating the metal; Electrochemically thickening the thickness of the remaining portion of the metal to provide the conductor to the support rod. 제13항에 있어서, 상기 금속을 레이저 또는 UV 방사에 의해 그 두께 전체를 국부적으로 제거하거나 또는 절연하는 것을 특징으로 하는 방법.The method of claim 13, wherein the metal is locally removed or insulated entirely from its thickness by laser or UV radiation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000987A 1990-01-23 1991-01-21 Semoconductor device comprsing a support method of manufacture it and method of manufacture the support KR100198209B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL9000161 1990-01-23
NL9000161A NL9000161A (en) 1990-01-23 1990-01-23 SEMICONDUCTOR DEVICE CONTAINING A CARRIER AND METHOD FOR MANUFACTURING THE CARRIER.

Publications (2)

Publication Number Publication Date
KR910015038A true KR910015038A (en) 1991-08-31
KR100198209B1 KR100198209B1 (en) 1999-07-01

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KR1019910000987A KR100198209B1 (en) 1990-01-23 1991-01-21 Semoconductor device comprsing a support method of manufacture it and method of manufacture the support

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US (1) US5198886A (en)
EP (1) EP0439227B1 (en)
JP (1) JP3040501B2 (en)
KR (1) KR100198209B1 (en)
CN (1) CN1024731C (en)
DE (1) DE69127910T2 (en)
NL (1) NL9000161A (en)

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Also Published As

Publication number Publication date
CN1054334A (en) 1991-09-04
EP0439227A1 (en) 1991-07-31
DE69127910T2 (en) 1998-04-02
JP3040501B2 (en) 2000-05-15
KR100198209B1 (en) 1999-07-01
JPH04212431A (en) 1992-08-04
NL9000161A (en) 1991-08-16
US5198886A (en) 1993-03-30
EP0439227B1 (en) 1997-10-15
CN1024731C (en) 1994-05-25
DE69127910D1 (en) 1997-11-20

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