KR910014831A - Sales Order Maintenance Circuit of Poster Terminal - Google Patents

Sales Order Maintenance Circuit of Poster Terminal Download PDF

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Publication number
KR910014831A
KR910014831A KR1019900000499A KR900000499A KR910014831A KR 910014831 A KR910014831 A KR 910014831A KR 1019900000499 A KR1019900000499 A KR 1019900000499A KR 900000499 A KR900000499 A KR 900000499A KR 910014831 A KR910014831 A KR 910014831A
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KR
South Korea
Prior art keywords
signal
interrupt
obr
data
generating
Prior art date
Application number
KR1019900000499A
Other languages
Korean (ko)
Other versions
KR920006281B1 (en
Inventor
윤석천
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019900000499A priority Critical patent/KR920006281B1/en
Publication of KR910014831A publication Critical patent/KR910014831A/en
Application granted granted Critical
Publication of KR920006281B1 publication Critical patent/KR920006281B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Cash Registers Or Receiving Machines (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

내용 없음No content

Description

포스터미널의 판매순서 유지회로Sales Order Maintenance Circuit of Poster Terminal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 판매정보에 대한 인터럽트 회로도, 제4도는 제3도의 구체회로도, 제5도는 제3도 및 제4도의 동작 파형도.3 is an interrupt circuit diagram for sales information of the present invention, FIG. 4 is a detailed circuit diagram of FIG. 3, and FIG. 5 is an operation waveform diagram of FIGS.

Claims (1)

판매정보 발생장치인, 키보드, OBR,MCR등의 입력 장치와, 인터럽트 신호에 의해 데이타 버스상의 정보를 리드하여 처리하는 제어부, 상기 입력장치들로 부터 발생되는 인터럽트 요구신호에 대한 인지신호를 발생하는 동시에 상기 CPU로 이를 알리는 인터럽트 제어부와, 상기 인터럽트 요구신호와 인지신호 발생시 상기 CPU로 인터럽트 신호를 발생하는 수단을 구비한 포스터미널의 판매순서 유지회로에 있어서, 상기 데이타 버스상의 판매정보 데이타를 입력하여 OBR 앤드데이타 검출시 OBR종료신호를 발생하는 수단과, 상기입력장치의 직렬데이타가 데이타 버스상에 병렬 데이타로 실리는 주기를 카운트하여 상기 OBR 종료신호의 통로를 인에이블 시키는 수단과, 상기 OBR의 인터럽트 인지신호 발생기 제1제어 신호를 래치하고,상기 OBR 종료신호 발생시 제1제어 신호를 제2제어 신호로 천이하는 수단과, 상기 키보드 및 MCR과 인터럽트 신호발생 수단 사이에 연결되어 상기 제2제어 신호발생시 인터럽트 통로를 형성하고 제1제어 신호발생기 차단하는 수단을 구비하여 입력장치에서 발생하는 판매정보의 길이에 관계없이 발생순서를 유지시켜 정보를 처리할 수 있도록 동작함을 특징으로 하는 포스터미널의 판매순서 유지회로.An input device such as a keyboard, OBR, MCR, a sales information generating device, a control unit that reads and processes information on a data bus by an interrupt signal, and generates an acknowledgment signal for an interrupt request signal generated from the input devices. In the sales order maintaining circuit of Foster Terminal, which has an interrupt control unit for notifying the CPU of the same, and means for generating an interrupt signal to the CPU when the interrupt request signal and acknowledgment signal are generated, the sales information data on the data bus is inputted. Means for generating an OBR end signal upon detection of OBR end data, means for enabling the passage of the OBR end signal by counting a period in which serial data of the input device is carried as parallel data on a data bus, and Latches a first control signal for an interrupt acknowledgment signal generator; Means for transitioning a signal to a second control signal, and means for transitioning between said keyboard and said MCR and an interrupt signal generating means to form an interrupt passage when said second control signal is generated and to block said first control signal generator in said input device. A sales order maintenance circuit for poster terminal, characterized in that it operates to process information by maintaining a generation order regardless of the length of sales information that occurs. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900000499A 1990-01-17 1990-01-17 Circuit for queue maiutenance on pos terminal KR920006281B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900000499A KR920006281B1 (en) 1990-01-17 1990-01-17 Circuit for queue maiutenance on pos terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900000499A KR920006281B1 (en) 1990-01-17 1990-01-17 Circuit for queue maiutenance on pos terminal

Publications (2)

Publication Number Publication Date
KR910014831A true KR910014831A (en) 1991-08-31
KR920006281B1 KR920006281B1 (en) 1992-08-03

Family

ID=19295341

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900000499A KR920006281B1 (en) 1990-01-17 1990-01-17 Circuit for queue maiutenance on pos terminal

Country Status (1)

Country Link
KR (1) KR920006281B1 (en)

Also Published As

Publication number Publication date
KR920006281B1 (en) 1992-08-03

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