KR910012960A - Hold Acknowledgment Signal Synchronization Circuit - Google Patents

Hold Acknowledgment Signal Synchronization Circuit Download PDF

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Publication number
KR910012960A
KR910012960A KR1019890020152A KR890020152A KR910012960A KR 910012960 A KR910012960 A KR 910012960A KR 1019890020152 A KR1019890020152 A KR 1019890020152A KR 890020152 A KR890020152 A KR 890020152A KR 910012960 A KR910012960 A KR 910012960A
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KR
South Korea
Prior art keywords
memory access
direct memory
synchronization circuit
acknowledgment signal
signal synchronization
Prior art date
Application number
KR1019890020152A
Other languages
Korean (ko)
Other versions
KR930007683B1 (en
Inventor
현종웅
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR8920152A priority Critical patent/KR930007683B1/en
Publication of KR910012960A publication Critical patent/KR910012960A/en
Application granted granted Critical
Publication of KR930007683B1 publication Critical patent/KR930007683B1/en

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Abstract

내용 없음.No content.

Description

홀드 에크놀리지 신호 동기화회로Hold Acknowledgment Signal Synchronization Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 회로도,2 is a circuit diagram of the present invention,

제5도는 본 발명의 동작파형도.5 is an operational waveform diagram of the present invention.

Claims (1)

고성능 퍼스널 컴퓨터의 다이렉트 메모리 억세스동기화 회로에 있어서, 다이렉트 메모리 억세스 컨트롤러의 버스요구시CPU로 부터 발생되는 홀드 에크놀리지 신호를 입력하여 소정 제어 신호의 상태에 따라 상기 다이렉트 메모리 억세스 컨트롤러로 다이렉트 메모리 억세스 어크날리지 신호를 발생하는 제1제어수단과, 버스컨트롤러로부터 발생되는 제1리세트 제어신호를 입력하여 상기 제1제어수단의 다이렉트 메모리억세스 완료시에만 CPU리세트 신호를 발생하는 제2제어 수단으로 구성됨을 특징으로 하는 회로.In a direct memory access synchronization circuit of a high-performance personal computer, the hold memory signal generated from the CPU when a bus of the direct memory access controller is input is input, and the direct memory access controller is input to the direct memory access controller according to the state of a predetermined control signal. A first control means for generating a signal and a second control means for inputting a first reset control signal generated from a bus controller to generate a CPU reset signal only upon completion of direct memory access by the first control means. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8920152A 1989-12-29 1989-12-29 Circuit for syncronizing a acknowledge signal in memory controller KR930007683B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR8920152A KR930007683B1 (en) 1989-12-29 1989-12-29 Circuit for syncronizing a acknowledge signal in memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR8920152A KR930007683B1 (en) 1989-12-29 1989-12-29 Circuit for syncronizing a acknowledge signal in memory controller

Publications (2)

Publication Number Publication Date
KR910012960A true KR910012960A (en) 1991-08-08
KR930007683B1 KR930007683B1 (en) 1993-08-18

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ID=19294183

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8920152A KR930007683B1 (en) 1989-12-29 1989-12-29 Circuit for syncronizing a acknowledge signal in memory controller

Country Status (1)

Country Link
KR (1) KR930007683B1 (en)

Also Published As

Publication number Publication date
KR930007683B1 (en) 1993-08-18

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