KR910012966A - System Bus Interface Subunit - Google Patents

Abstract

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Description

System Bus Interface Subunit

As this is a public information case, the full text was not included.

1 is a block diagram of the present invention,

2 is a block diagram of a local arbiter of the present invention;

3 is a block diagram of a system bus cycle controller of the present invention.

Claims (7)

The local arbiter 1 which arbitrates the call of the system bus, the line selector 2 connecting the local signal line and the signal line of the system bus, and the transaction line given by the two local bus cycle controllers 3 and 3a. To the system bus cycle controller 4 which outputs the necessary control signals when performing, to the system bus arbiter 5 to request and mediate the use of the system bus, to registers SSR0, SSR1, SSR2, SSR7, etc. The system status register (6) consisting of the system controller (7) consisting of registers (SSR0), (SSR2), (SSR6) (SSR7), etc. to perform the operation delegated from two local buses without error. Bus interface subunit. The system of claim 1, wherein one system bus cycle controller is connected to two local bus cycle controllers, so that if a request for use of the system bus is first requested from one of the two local bus cycle controllers, the local bus arbiter selects a line selector. System bus interface subunit, which allows to perform a transaction on the system bus after being licensed. According to claim 1, When the local arbiter requesting the use of the line selector unit outputs a signal (local-grant) and the signal indicating that the busy (LSH-busy) to inform the other local bus cycle controller that the line selector is busy. System bus interface subunit. The read transaction in the normal state of the system bus includes the steps of reading the start of a read transaction, checking whether the first parity error state (lst-dperr) of the address phase, requesting the use of the system bus, obtaining permission, and controlling A system bus interface for outputting signals (drive-addr) and (latch-aack) and terminating the cycle while outputting a response signal (local-stop) when a transaction is executed without a parity error. Sub unit. 5. The system bus interface subunit according to claim 4, wherein the control signal (latch-data) is output only when the input data is identical to the identification data of the system status register (SSR7). The system of claim 4, wherein the second parity error state (2nd-apperr) (2nd-dperr) occurs and the cycle is terminated with the retry timeout bit (Ro) of the system status register (SSR1) set to "0". Bus interface subunit. The write transaction in the normal ecology of the system bus includes the steps of checking whether the write transaction is at the beginning of a write or first parity error state (lst-apperr or lst-dperr), making a request to use the system bus, and obtaining permission. Outputting control signals (drive-addr), (drive-data), and (latch-data) sequentially; if a transaction is executed without a parity error, outputs a control signal (datch-dack) and sends a response signal (local The system bus interface subunit allows the process to proceed by terminating the cycle with the output of -stop). ※ Note: The disclosure is based on the initial application.