KR920002664B1 - System bus control method in multiprocessing system - Google Patents

Abstract

The system includes a local arbiter (1), a line selecting section (2), a pair of local bus cycle controllers (3)(3a), a system bus cycle controller (4), a system arbiter (5), a system status register (6), a system controller register (7), and a system bus adaptor (8). If any one of the local bus cycle controllers gives a request for the use of a system bus, the local bus arbiter obtains a permission to use the bus from the line selecting section (2), and then, carries out a transaction on the system bus. If the system bus is busy, the local arbiter outputs a busy signal to other local bus cycle controllers to inform that the line selecting section is busy.

Description

System Bus Control Method of Multiprocessing System

1 is a block diagram of a multiprocessing system to which the present invention is applied.

FIG. 2 is a block diagram showing the input / output relationship of the local arbiter shown in FIG.

3 is a block diagram showing the input / output relationship of the system bus cycle controller shown in FIG.

4 is a flowchart showing the cycle establishment according to the present invention made between two local bus cycle controllers and one system bus cycle controller.

5 is a flowchart showing the progress of a normal read transaction in the system bus according to the present invention.

6 is a flowchart showing a state in which a system bus according to the present invention performs a normal write transaction.

* Explanation of symbols for main parts of the drawings

1: Local arbiter 2: Line selector

3, 3a: Local bus cycle controller 4: System bus cycle controller

5: system bus arbiter 6: system status register

7: system control register

The present invention relates to a system bus control method in a multi-processing system, and more particularly, to a control method for interfacing a system bus that is connected to two local bus cycle controllers to perform an operation delegated from them and informs the result thereof. will be.

In a multiprocessing system, a plurality of processors exist, and each processor module must have one local bus cycle controller due to a local bus that is separated from each other independently, and the system bus interface is shared by two processor modules.

Therefore, each operation performed by two processors performs the operation delegated by the local bus cycle controller without error according to its own system check or authorization of information transfer through the system bus, and performs an arbitration phase when the other processor is in use. There was a problem such that the configuration of the local bus cycle controller and the system bus interface is complicated, as well as malfunction due to heavy signal transmission.

Accordingly, an object of the present invention is to provide a control method for interfacing a system bus that performs an operation delegated by two local bus cycle controllers without errors.

Accordingly, the multi-processing system to which the present invention is applied is requested to use the system bus from the system bus cycle controller to the system bus arbiter when the local bus cycle controller is delegated to perform the corresponding operation. Continues the arbitration phase until it is received, and if a license is obtained, it performs the cycle of the given operation according to the information transfer protocol of the system bus, and informs the local bus cycle controller when the cycle is completed without error. If a problem such as a parity error occurs during execution, retry or interrupt.

The present invention will be described in detail with reference to the accompanying drawings as follows.

1 shows a configuration of a multi-processing system to which the present invention is applied. The local arbiter 1 arbitrates between two processor modules in a state where one system bus is called, a local signal line and a system bus of two processor modules. A system for outputting a control signal required for performing a transaction given by the two local bus cycle controllers (3) and (3a) to match the protocol of the system bus. The bus cycle controller 4, the system bus arbiter 5 which receives the request signal from the system bus cycle controller 4, starts the arbitration and sends a permission signal upon completion, an error that occurs during the operation of the system, the system bus interface sub Errors that occur in the unit, the state of the system bus interface subunit, and the processor to distinguish A system status register (6) consisting of registers (SSR0), (SSR1), (SSR2), (SSR7), and the like for storing star data (IDs), information for controlling system operation, and a system bus interface subunit. It consists of registers (SCR0), (SCR2), (SCR6), and (SCR7) which store information to control, information to control the operation of the system bus interface subunit, and information to control the time to wait for data during the read operation. The system control register 7 and the system bus adapters 8, which are buffers of portions at which signal lines of the system bus are input and output, are configured.

2 shows the function of a local arbiter. When a request signal (local-reql) 2 for using the line selector 2 is input from a local bus cycle controller of each processor module, the line selector 2 is inputted. Snooping controller controller (not shown) outputs a signal (LSM-busy) indicating that it is in use while outputting a local-grant only when not in use. When snooping for cache coherence is performed in the system, when a signal (LSM-locked) is used to transfer an address bus on a system bus to a local bus, -grant).

Cache coherence means that the data in the main memory and the same data located in each of the cache memories always have the same value.

That is, since the data located in the cache memory is a form of copying some of the data located in the main memory, the data of the main memory and the corresponding data in the multiple cache memories copied and located must always be identical. If one data is changed to another and the rest of the data is not changed to the new value, the result of the calculation using the data is incorrect.

Thus, the cache coherence must be maintained. When several identical data are copied to several cache memories, when one of the data is changed to a new value, this is a write operation when viewed on the bus.

The stuping is one of the necessary methods for maintaining the cache coherence, and if the data is changed by a write operation while continuously observing the bus in the remaining cache memory, each of the same data to the new same value By changing or invalidating, you maintain coherence between multiple copies of data. In this case, the method of continuously observing the bus is called bus snooping.

3 shows the function of a system bus cycle controller, which exists as a slave device to the local bus cycle controller.

When the signal for starting a transaction (local-start) and the type of transaction (local-read) or (local-write) are input from the local bus cycle controller, the system bus arbiter can be used for the use of the system bus. After receiving the SC-grant by sending the request signal SC-req, receiving the SC-grant, and then outputting the control signals described below to the local bus cycle controller when the transaction is terminated. Send a response signal (local-stop).

Among the signals output from the controller 4, the drive-addr signal is a control signal for outputting each signal used in the address phase including the address signal of the system bus, and the drive-data signal is used in the data signal and the data phase of the system bus. A control signal for outputting each signal used, the latch-date signal is a control signal for latching each signal input in the data phase, the latch-aack and latch-dack signal is a response phase during the system bus protocol The control signals are for counting the corresponding bits of the register according to the result of the address acknowledgment signal or the data response signal transmitted to the lach-status signal. The lach-status signal outputs the status information necessary for cache coherence to the system bus. Control signal.

The controller 4 receives necessary information from each device or control register of the system. The types of the controller 4 are as follows.

The read-ssrO signal is an input signal to reset its contents as soon as the processor reads the value of a register belonging to a bit of a system status register (SSRO) that stores an error that occurred during system operation. This-modale signal is a data phase. This is an input signal asserted when the data transmission signal sent with the data is equal to the wall data of the system status register SSR7 that stores identification data for identifying the processor.

The dp-error and ap-error signals are input signals asserted when a parity error occurs in the data phase and the address phase. When the signals are input, the system status register (SSR2) stores the state of the system bus interface subunit. The data phase bit (DP) and the address phase (AP) are set. If it is already set, the retry time out of the system status register (SSR1) that stores an error occurring in the system bus interface subunit is set. Resetting the data phase bit (DP) and the address phase bit (AP) while setting the bit (RO).

The busy-count-out signal is asserted after a failed number of retries given to the system control register (SCR6), which stores information that controls the operation of the system interface subunit. If this signal is asserted, the system status register is asserted. Set the busy timeout bit (BO) of (SSR1).

The read-count-out signal is asserted when a given amount of time has elapsed in the system control register (SCR7), which stores information that controls how long a read transaction begins and waits for data, when it is asserted. If no data is inputted before, set the count out bit (RC) in the system status register (SSR1).

The data phase bit DP and the address phase bit AP of the system status register SSR2 are used to perform one retry, to determine whether the parity error occurred is first or second.

The read count enable bit RE and the busy count enable bit BE of the system control register SCR2 enable the counts of the values given to the system control registers SCR7 and SCR6, respectively. RE) and (BE) are not used when the system control registers (SCR7) and (SCR6) are reset.

If the reset bit RS is set, the entire system bus interface subunit is reset. In the snoop control subunit (not shown), the state signals IM (GL) (SNACK) following the cache coherency are input.

4 is a flowchart showing the establishment of a cycle between two local bus cycle controllers and one system bus cycle controller.

In FIG. 4, a signal indicating a start of a transaction by the first local bus cycle controller (local-startl), a first shared area signal (shared-spacal), and a signal indicating the type of a transaction (local-readl or local). writel) is entered (step 10), it is checked whether the system-grant signal (local-grantl) of the system bus is input from the system bus cycle controller 4 (step 11) until it is entered. After waiting (step 12), when a grant signal (local-grantl) is input (step 13), a cycle of operation is performed according to the information transfer protocol of the system bus according to a given transaction (step 14).

Check if the cycle has been performed normally without problems such as parity error (step 15), and if completed, output the response signal (local-stop) to the first local bus cycle controller and then cycle to the first local bus cycle controller. End (step 16).

Meanwhile, in step 10, a signal for notifying the start of a transaction (local-start2), a second shared area signal (shared-space ² ), and a type of a transaction are notified when a signal for the first local bus cycle controller is not input. If both signals (local-read2 or local-write2) are input (step 17), the second local bus cycle controller is in a state of using the system bus, so the system bus's license signal (local-grant2) is input. (Step 18), if not input, wait until input (step 19), and if a grant signal (local-grant2) is input (step 20), the operation of the system bus signaling protocol is performed according to a given transaction. Perform the cycle (step 21).

After checking whether the cycle is normally performed without a problem of parity error or the like (step 22), if it is completed, the cycle for the second local bus cycle controller is terminated while outputting a response signal (local-stop) to the second local bus cycle controller. (Step 23)

5 is a diagram illustrating a state in which a read transaction is performed in a normal state of a system bus, and illustrates a process of establishing a transaction and generating an error.

The start of a read transaction in which both a local-start signal and a kind signal (local-read) and a local-grant signal are input, or a signal of an address phase (AP). Is inputted and the first parity error state (lst-aperr) where an address parity error occurs (step 30), after outputting a system bus use request signal (SC-req) through the system bus arbiter (step 31), is granted. Wait for the signal SC-grant to be input (step 32), wait until the permission signal is not input (step 33), and output the signals used in the address phase when the grant signal (SC-grant) is input. Address cycle 0, which outputs a control signal (drive-addr), is performed (step 34).

In response to the result of the response signal transmitted in the answer phase, address cycle 1 for outputting a control signal (latch-aack) for latching the corresponding bit of the register is performed (step 35).

어드레스 페이즈에서 패리티 에러가 발생한 두번재 패리티 에러상태(2nd-aperr)가 되면(단계 36)두번째 패리티 에러 사이클을 수행한다(단가 38).If a parity error (lst-aperr) occurs in the first address phase (step 36), the address phase bit (AP) of the system status register SSR2 is set to '0' (step 37). On the other hand, without entering the address phase

When the second parity error state (2nd-aperr) where the parity error occurs in the address phase (step 36), a second parity error cycle is performed (unit price 38).

If the input signal (ap-error) of the assertion for the parity error is not input (step 36), the data transmission is awaited (step 39). If no data is input for a certain period of time (step 39-1), the watch dog time out bit (To) of the system status register (SRR0) is set to 0 (step 39-2). Is returned to the state of.

Check that the input data is the same as the identification data of the system status register SSR7 (step 40) and output a control signal (latch data) for latching the respective signals only when the data is identical (step 41).

데이타 페이즈에서 패리티 에러가 발생한 두번째 패리티 에러상태(2nd-dperr)가 되면(단계 42), 단계 36에서의 경우와 동일하게 시스템 상태 레지스터(SSR1)의 리트라이 타임아웃 비트(Rerty Time Out)(Ro)를 ＂0＂으로 하는 두번째 패리티 에러 사이클을 수행하는 한편(단계 38), 패리티 에러에 대한 입력신호(Parity-error)가 없으면(단계 42) 사이클의 종료를 의미하는 응답신호(local-stop)를 출력한 다음(단계 44), 트랜잭션의 시작을 알리는 신호(local-start)가 입력되지 않은 경우에만(단계 45)단계 38을 수행한 경우와 같이 처음의 상태로 귀환하는 것이다.If a parity error (Ist-dperr) occurs in the first data phase (step 42), the data phase bit (DP) of the system status register (SSR2) is set to '0' (step 43), and then returned to the initial state. Without entering a data phase

When the second parity error state (2nd-dperr) in which the parity error occurs in the data phase (step 42) occurs, the retry timeout bit (Rerty Time Out) (Ro) of the system status register SSR1 is performed in the same manner as in step 36. C) performs a second parity error cycle with " 0 " (step 38), and if there is no input signal (parity-error) for the parity error (step 42), a response signal (local-stop) indicating the end of the cycle. After outputting (step 44), it returns to the initial state as in the case where step 38 is performed only when a signal (local-start) indicating the start of a transaction is not input (step 45).

6 is a diagram illustrating a state where a write transaction proceeds in a normal state of a system bus, and illustrates a process of establishing a transaction and generating an error.

The start of a write transaction (local-start) and a signal (local-write) and a grant (local-grant) that inform the start of a transaction are input, or a signal of an address phase is input. (AP) First parity error (ap-error) occurs in the address phase (1st parity error status (lst-aperr) or data signal input, the first parity error (dp-error) occurs in the DP) If the parity error state (lst-dperr) (step 50), outputs the use request signal (sc-req) of the system bus through the system bus arbiter (step 51), and waits for the input of the grant signal (SC-grant). Perform an address cycle of outputting a control signal (drive-addr) for outputting the address signal of the system bus and the signals used in the address phase only when (step 52) is input (step 53), A data cycle of outputting a control signal (drive-data) for outputting the data signals of the system bus and the signals used in the data phase is performed (step 54).

어드레스 페이즈에서 패리티 에러가 발생하는 두번째 패리티 에러상태(2nd-aperr)이면(단계 56), 시스템 상태 레지스터(SSR1)의 리트라이 타임아웃 비트(R0)를 ＂0'으로 하면서 사이클의 종료를 의미하는 응답신호(local-stop)를 출력하는 두번째 패리티 에러사이클을 수행한다(단계 58).After performing an address response cycle of outputting a control signal (latch-aack) for setting the corresponding bit of the register according to the result of the address response signal (step 55), if the first parity error state of the address is compared by comparing the input states (Step 56), while returning to the initial state while setting the address phase bit AP of the system status register SSR2 to '0' (step 57), the signal of the address phase is not input.

If the second parity error state (2nd-aperr) where a parity error occurs in the address phase (step 56), the retry timeout bit (R0) of the system status register (SSR1) is set to '0' to signify the end of the cycle. A second parity error cycle is output, which outputs a response signal (local-stop) (step 58).

(단계 56), 데이타 응답신호의 결과에 따라 레지스터의 해당비트를 셋시키기 위한 콘트롤신호(Iatch0dack)를 출력하는 데이타 응답 사이클을 수행한다(단계 59).And if there is no input of assertion for parity error in address phase

In step 56, a data response cycle for outputting a control signal Iatch0dack for setting the corresponding bit of the register is performed in accordance with the result of the data response signal (step 59).

데이타 페이즈에서 패리티 에러가 발생하는 두번째 패리티 에러상태(2nd-dperr)이면(단계 60), 단계 58의 두번째 패리티 에러사이클을 수행하며, 데이타 페이즈에서 패리티 에러에 대한 어서트의 입력이 없으면(이미지)(단계 60), 사이클의 종료를 의미하는 응답신호(local-stop)를 출력하면서 단계 58 및 61을 수행한 상태와 마찬가지로 처음의 상태로 귀환하는 것이다.If the first parity error state (lst-dperr) occurs when the data phase signal is input (DP) and a parity error occurs in the data phase after performing a data response cycle (step 60), the system status register Set the data face bit (DP) of (SSR2) to 0 (step 61) and the data phase signal is not input.

If there is a second parity error state (2nd-dperr) where a parity error occurs in the data phase (step 60), the second parity error cycle of step 58 is performed, and if there is no input of an assertion for the parity error in the data phase (image) (Step 60), it returns to the initial state similarly to the state of performing steps 58 and 61 while outputting a response signal (local-stop) indicating the end of the cycle.

Thus, the present invention comprises a local arbiter 1, a line selector 2, a system bus cycle controller 4, a system bus arbiter 5, a system status register 6 and a system control register 7 When one of the two local bus cycle controllers (3) and (3a) is delegated to perform the operation, it requests the use of the system bus and performs the given cycle of operation in accordance with the protocol of information transfer. In case of occurrence of a retry or interrupt dissociation, if the cycle is completed without error, the local bus cycle controller is notified. Thus, according to the present invention, several processors (local bus masters) exist on the same board. Another processor board memory board or I / O board connected to the system bus through one system bus interface. In and if it is desired to perform efficient transaction cycles with other board like, can give to map the local bus cycle, the system bus cycles effectively.

Generally, the processor defines a unique transaction cycle for data communication with the outside. In the present invention, when several of these transaction cycles exist on the same board, they are re-mapped by the local bus cycle controller to the local cycle. Local cycles can be mapped to system bus transaction cycles by the system bus cycle controller to ensure efficient operation without errors in the overall system configuration.

Claims (4)

Perform a transaction given by the local arbiter 1, which arbitrates the call of the system bus, a line selector 2 connecting the local signal line and the signal line of the system bus, and two local bus cycle controllers 3, 3a. A system bus cycle controller (4) which outputs the necessary control signals, a system bus arbiter (5) which requests and mediates the use of the system bus, and registers (SSR0), (SSR1), (SSR2) and (SSR7). A system status register 6 composed of the back and the like, system controller registers 7 composed of the registers SCR0, SCR2, SCR6, SCR7, etc. In a multiprocessing system comprising an in-system bus adapter (8), if a request for use of the system bus is requested from either of the two local bus cycle controllers first, a line selector from the local bus arbiter may be used. After receiving the license, perform the cycle establishment step to execute the transaction on the system bus, but the local arbiter outputs a local-grant and a signal (LSH-busy) indicating that it is in use when a request is made to use the line selector. To inform other local bus cycle controllers that the line selector is in use. The method according to claim 1, further comprising the step 30 of checking the start of a read transaction, whether the first parity error state (lst-dperr) of the address phase, and the request for use of the system bus and acquiring permission (31 to 3). 32), and outputting the control signals (drive-addr) and (latch-aack) (35), and if the assert input signal (ap-error) for the parity error is not input after a predetermined time elapsed Outputting a control signal (latch-data) only if the data is identical to the identification data of the system status register (SSR7) (36-41), and if a transaction is performed without an input signal for a parity error, a response signal (local adding a read transaction function in the normal state, comprising the steps 42 to 45 of terminating the cycle while outputting -stop). The method as claimed in claim 2, wherein when the second error state (2nd-aperr) or (2nd-dperr) occurs, the cycle is terminated with the retry timeout bit Ro of the system status register SSR1 set to '0'. A control method for a system bus, comprising adding (38). The method of claim 1, further comprising: checking whether a write transaction is started or a first parity error state (lst-aperr) or lst-dperr; 51 to 52, and sequentially outputting control signals (drive-addr), (drive-data), and (latch-data) (53 to 55) and control signals (latch-) when a transaction is performed without a parity error. and a write transaction function in the normal state, comprising steps 56 to 62 ending the cycle while outputting a dack) and outputting a response signal (local-stop).

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