KR910007750B1 - Method and apparatus for implementing multigle lock indications in a multiprocessor computer system - Google Patents

Abstract

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Description

[Name of invention]

Method and apparatus for implementing multi-lock indicator in multiprocessor computer system

[Brief Description of Drawings]

1 is a block diagram of a data processing system using the present invention.

2 is a block diagram of a node in the FIG. 1 data processing system.

3 is a timing diagram illustrating timing signals used in the FIG. 1 data processing system.

4 is a block diagram of the data interface 61 at the node of FIG.

5 is a block diagram of an arbiter in the FIG. 1 data processing system.

FIG. 6 is a timing diagram illustrating signals that appear on the FIG. 1 system bus during an interlock read transaction.

7 is a block diagram of a processor node in the FIG. 1 data processing system.

8 is a block diagram of a memory node in the FIG. 1 data processing system.

9 is a block diagram of a lock controller in the FIG. 8 memory node.

Detailed description of the invention

[Background of invention]

TECHNICAL FIELD The present invention relates to a computer system, and more particularly to a computer system having multiple processors interconnected by a suspended bus.

Existing computer systems may have multiple processors, memory resources, and input / output (I / O) devices interconnected by a common bus in order to achieve high performance overall computing power. Such a configuration can provide a high performance system capable of executing millions of instructions per second. However, interconnecting multiple processors can cause difficulties when it is desired to perform an instruction sequence known as a read-modify-write (RMW) operation. In an RMW operation, one processor retrieves data from a memory location, performs operations on that data, and writes the modified data back to the original memory location. If one processor initiates an RMW operation on one memory location, unpredictable results affect data integrity, and the second processor writes and reads the RMW operation of the first processor. In the inter-term period, an RMW operation is attempted for the same memory location.

One way to prevent multiple processors from performing RMW operations at the same memory location is to provide interlock read capability. It uses a block indicator, such as the lock bit, which is set when the read part of the RMW operation is performed and reset after the write portion of the RMW operation is finished. The second processor, which attempts to initiate an RMW operation at a location in memory when the lock bit is set, causes the memory to be idled or retried for a predetermined number of bus cycles after the second processor issues an interlock read command. The lock status information is returned. Busy acknowledgment indicates to the processor that the second interlock read command was not allowed by the memory.

The interlock read operation alleviates the problems caused by the multiple processors wishing to perform the RMW operation respectively. Processors are granted effective access to the bus during such interlock read operations, for example by arbitration processing using a round robin algorithm. Nevertheless, however, performance failure may still occur. For example, under certain bus traffic conditions, a particular processor may repeatedly encounter a locked memory location and may not be able to obtain the necessary access to memory resources in a timely manner. Such problems can be reduced by providing multiple lock bits to the memory node, where each lock bit is associated with a portion of the memory node rather than the entire memory node. Such multiple lock bits will provide a more sophisticated granularity of interlocked read operation on the memory node, constraining a smaller portion of memory after the interlock read operation. This solution also allows for a higher success rate of RMW operation and thus improves system throughput. However, performing multiple lock bits in the prior art pending bus multiprocessor system makes the circuitry for detecting and transmitting lock state information unacceptably complex.

Although the above description emphasizes the operation of a computer system utilizing processor nodes, memory nodes and I / O nodes, a more general description of such a system is a commander node, i.e., a node and a responder node that initiates a transaction on a bus, i. It relates to a node that responds to a transaction initiated by an existing node. In many operations, a single device can function as a commander node or responder node.

It would be desirable to provide a computer system in which elements each having different characteristics are interconnected through several buses. However, this was very difficult for lock state information to be performed in the prior art Pendiverse system with a read command that was initially interlocked.

Overview of the Invention

It is a first object of the present invention to provide a responder node in a multiprocessor system having multiple lock bits and a simplified circuit for transmitting lock state information.

It is a second object of the present invention to provide a responder node in a multiprocessor pending bus computer having an interlock read operation in which lock state information is not transmitted in a fixed time relationship with an initial interlock read command.

Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be taught by the practice of the invention. The objects and advantages of the invention may be achieved even if they can be realized by means and combinations particularly pointed out in the appended claims.

The present invention overcomes the problems and disadvantages of the prior art by providing a responder node that generates an acknowledgment for a predetermined time after an interlock read command and generates a lock status message at a non-specific time after the interlock or message.

According to the principles of the present invention, there is provided an apparatus for performing an exclusive read-modify-write operation on a fenced bus, the operation of retrieving information stored at a specific location and by means of a subsequent interlock read command. It has a series of different transactions on the pending bus that includes an interlock read command to restrict access to the data and an unlock write command to store information at that particular location and restore access to the stored information. The apparatus includes means for receiving an interlock read command from the commander node; Storage means including a specific position for storing information; Lock means coupled with the storage means, the lock means operable between the locked state in an unlocked state to allow access to the storage means in the unlocked state and to deny access to the storage means in the locked state; In response to the interlock read command, interlock read command means for generating a lock status indication indicative of the status of the lock means and for switching the lock means from the unlocked state to the locked state; In response to the unlock write command, unlock write command means for storing the modified information at a specific position and for switching the lock means from the locked state to the unlocked state; And status response means for transmitting a lock status message comprising a lock means status at a non-specified time following the interlock read command to the commander node that issued the interlock read command.

In addition, the present invention provides a method for responding to an exclusive read-modify-write operation on a fenced bus, the operation of which retrieves information stored at a particular location and writes the information to the stored information by a subsequent interlog read command. It has a series of different transactions on the pending bus that includes an interlock read command for restricting access to and an unlock write command for storing information at that particular location and restoring access to the stored information. The method includes receiving an interlock command from the commander node, transmitting an acknowledgment to the commander node at a predetermined time subsequent to the commencement of the command indicating receipt of the interlock read command, checking the lock indicator to indicate the lock. Switching the lock indicator from an unlock state to a lock state if the self is in the unlock state, and transmitting a lock state signal corresponding to the lock indicator state to the commander node at a non-specific time following the initiation of the interlock read command. And storing the modified information in a specific position and switching the lock indicator from the locked state to the unlocked state upon receipt of the unlock write command.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one embodiment of the invention and, together with the description, explain the principles of the invention.

Detailed description of the preferred embodiment

A. System Overview

1 illustrates an embodiment of a data processing system 20 that implements the present invention. At the heart of the system 20 is the system bus 25, which is a synchronous bus that allows communication between several processors, memory subsystems, and I / O systems. Communication over the system bus 25 takes place synchronously using periodic bus cycles. The typical bus cycle time for the system bus 25 is 64 nsec.

In FIG. 1, a system bus 25 is coupled to two processors 31 and 35, a memory 39, one I / O interface 41 and one I / O device 51. In FIG.

In a preferred embodiment of the data processing system 20, a central arbiter 28 is also connected to the system bus 25. The arbiter 28 supplies certain timing and bus arbitration signals directly to other devices on the system bus 25 and shares certain signals with these devices.

The installation shown in FIG. 1 is a preferred embodiment and should not be taken as limiting the invention. For example, I / O device 53 may be coupled directly to system bus 25, and arbiter 28 need not operate in the manner described for the present invention.

In the terms used to describe the present invention, the processors 31 and 35, the memory 39, the I / O interface 41 and the I / O device 51 all refer to nodes. “Node” is defined as a hardware element connected to the system bus 25.

According to the terminology used to describe the present invention, the term “signal” or “line” is used interchangeably to refer to the name of a physical wire. The term "data" or "level" is used to refer to a value that a signal or line can take.

The node performs transmissions with other nodes via the system bus 25. “Delivery” is one or more adjacent cycles that share a common transmitter and a common arbiter. For example, a read operation initiated by one node to obtain information from another node on the system bus 25 requires sending a command from the first node to the second node, followed by a first node from the second node. Requires one or more return data transfers to the network.

A transaction is defined as a complete logical task performed on the system bus 25 and may include one or more transfers. For example, a read operation consisting of a command transfer followed by one or more return data transfers is a transaction. In a preferred embodiment of the system bus 25, an acceptable transaction supports the transmission of different data lengths and includes read, write (masked), interlock read, unlock write and interrupt operations. The difference between an interlock readout and a regular or non-interlock readout is that an interlock readout for a particular location retrieves the information stored at that location and subsequently restricts access to that stored information by an interlock readout command. Access restriction is performed by setting a lock mechanism. Subsequent unlock write commands restore the information at a particular location and restore access to the stored information by resetting the lock mechanism at that location. Thus, the interlock read / unwrite operation is in the form of a read-modify-write command.

Since the system bus 25 is a "pended" bus, it facilitates the efficient use of bus resources by having other nodes use the bus cycle consumed to wait for a response. In a fenced bus, one node may initiate a transaction and then another node may have access to the bus before the transaction ends. Thus, the node initiating the transaction does not bind the bus for the entire transaction time. This is in contrast to the non-pended bus, where the bus is bound during the entire transaction. For example, after a node initiates a read transaction and makes a command transfer on the system bus 25, the node to which the command transfer is directed may not immediately return the requested data. The cycle on bus 25 is then valid between the command transfer of the read transaction and the return data transfer. System bus 25 allows other nodes to use the cycles.

In using the system bus 25, each of the nodes may take a different role to influence the transmission of information. One of its roles is the “commander”, which is defined as the node that initiated the transaction in progress. For example, in a write or read operation, the commander is a node that requested a write or read operation and not necessarily a node that transmits or receives data. In the preferred protocol for the system bus 25, one node is maintained as the commander throughout the entire transaction, although another node may take ownership of the system bus 25 during any cycle of the transaction. For example, even if a node has control of the system bus 25 during a data transfer in response to sending a read transaction, that node will not be a commander on the bus. Instead, this node is called a responder.

The responder responds to the commander. For example, if the commander initiates a write operation to write data from node A to node B, then node B becomes a responder. Also, in the data processing system 20, the nodes can be commanders and responders at the same time.

The transmitter and receiver are the roles that nodes take on separate transmissions. "Transmitter" is defined as a node which is a source of information carried on the system bus 25 during transmission. “Receiver” is defined as a node that is in a complementary relationship with the transmitter and receives the information carried on the system bus 25 during transmission. During a read transaction, for example, the commander may first be a transmitter during command transmission and then a receiver during return data transmission.

When a node connected to the system bus 25 is required to be a transmitter on the system bus 25, the node has two request lines CMD REQ (commander) connected between the central arbiter 28 and that particular node. Assert) and RES REQ (responder request). In general, a node needs to be a commander and uses the CMD REQ line to initiate a transaction on the system bus 25, and uses the RES and REQ lines to become a responder to return data or messages to the commander. . Normally, the central arbiter 28 detects that the node requires access to the bus (ie, the request line is asserted). The arbiter then responds to one of its asserted request lines to grant corresponding node access to bus 25 according to the priority algorithm. In the preferred embodiment, the arbiter 28 maintains two separate circular queues, one for the commander request and the other for the responder request. Preferably, the responder request has a higher priority than the command request and is processed before the command request.

The commander request line and the responder request line are considered arbitration signals. As shown in FIG. 1, the arbitration signal is also a point-to-point interleave permit signal from the central mediator 28 to each node, a system bus extension signal for performing multibus cycle transmission, and a node such as a memory system. It contains a system bus erase signal to control the initiation of a new bus transaction when it cannot be momentarily maintained in traffic on the bus.

Other types of signals that may constitute the system bus 25 include information transmission signals, response signals, control signals, console / front panel signals, and some auxiliary signals. The information transmission signal includes a data signal, a function signal representing a function performed on a system bus during the current cycle, an identification signal identifying a commander, and a parity signal. The response signal generally includes an acknowledgment or confirmation signal from the receiver to control the status of the data transmission to the transmitter.

Control signals include warning signals, such as identifying low line voltage or low DC voltage, clock signals, reset signals used during initial setup, load failure signals, default signals used during idle bus cycles, and error default signals. The console / front panel signal enables signals to send and receive serial data to the system console, boot signals to control the behavior of the boot processor during power up, and modifications to the erasable PROM of the processor on the system bus 25. And a signal for supplying battery power for clocking logic on any node. In addition to the redundant signal, the auxiliary signal includes an identification signal that causes each node to form an identification code.

2 shows an embodiment of a node 60 connected to the system bus 25. Node 60 may be a processor, memory, I / O device, or I / O interface. In the embodiment shown in FIG. 2, node 60 includes a system bus interface 64 that incorporates node-specific logic 65, nodebus 67 and data interface 61 and clock decoder 63. Include. Preferably, data interface 61, clock decoder 63 and node bus 67 are standard components for nodes connected to system bus 25. The node specific logic 65 uses a different integrated circuit than the system bus interface 64, and preferably interfaces with the node bus 67 in addition to the circuits specified by the user to perform the node's specific functions. Includes standard circuitry for In general, data interface 61 is the main logic and electrical interface between node 60 and system bus 25, and clock decoder 63 provides timing signals to node 60 in accordance with a centrally generated clock signal. In turn, the nodebus 67 provides a high speed interface between the data interface 61 and the node specific logic 65.

In the preferred embodiment of node 60 and system bus interface 64 shown in FIG. 2, clock decoder 63 incorporates control circuitry for forming a signal to be carried on system bus 25, and the node The clock signal received from the central arbiter 28 is processed to obtain timing signals for the particular logic 65 and data interface 61. Since the timing signal obtained by the clock decoder 63 uses the clock signal generated at the center, the node 60 will operate in synchronization with the system bus 25.

3 is a timing diagram showing any one of one bus cycle, a clock signal received by the clock decoder 63 and timing signals generated by the clock decoder 63. FIG. The clock signals received by the clock decoder 63 include a time H signal, a time L signal and a phase signal as shown in FIG. The time H and L signals are the opposite of the base clock signals, and the phase signal is obtained by dividing the base clock signal by three. Timing signals generated by clock decoder 63 include C12, C23, C34, C45, C56 and C61, all of which are shown in FIG. These timing signals required by the data interface 61 (which occur once per bus cycle) are supplied to the data interface 61 and include an equivalent signal for the timing signals supplied to the data interface 61. A series of complete timing signals are buffered and supplied to node specific logic 65. The purpose of the buffering is to ensure that the node specific logic 65 improperly loads the timing signal, thereby not adversely affecting the operation of the system bus interface 64. The clock 63 is a six part cycle for each bus cycle. The clock signal is used to generate a signal, and then the subcycles are used to generate six timing signals CXY, where X and Y represent two adjacent subcycles combined to form one timing signal.

Each node in the system bus has a series of corresponding timing signals generated by the clock decoder 63. While the corresponding signals occur at exactly the same time from node to node through the system, the timing between the corresponding signals varies due to variations between the clock decoder 63 and other circuits at the multiple nodes. This timing variation is commonly known as "clock skew".

4 shows a preferred embodiment of the data interface 61. The data interface 61 incorporates a temporary memory circuit and a bus driving circuit to provide a bidirectional high speed interface between each of the lines of the node bus 67 and each of the lines of the system bus 25. As shown in FIG. 4, the data interface 61 preferably stores the memory elements 70 and 72 and the system bus driver 74 to provide a communication path from the node bus 67 to the system bus 25. FIG. Include. The data interface 61 also includes a memory element 80 and a node bus driver 82 to provide a communication path from the system bus 25 to the node bus 67. As used in the description of the data interface 61, the term " jade element " usually refers to a bistable memory element, such as a transparent latch or master-slave memory element, and does not refer to a particular facility. Those skilled in the art will appreciate that any type of memory element is suitable.

As shown in FIG. 4, the memory element 70 has an input connected to receive data from the node bus 67 and an output connected to the input of the memory element 72. As shown in FIG. The output of the memory element 72 is connected to the input of the system bus driver 74, and the output of this driver is connected to the system bus 25. The memory elements 70 and 72 are controlled by the node bus control signals 76 and 78, respectively, which are extracted from the timing signals generated by the clock decoder 63. The storage elements 70 and 72 provide two stages of temporary storage for pipelining data from the node bus 67 to the system bus 25.

System bus driver 74 is controlled by system bus driver enable 79. According to the state of the system bus driver enable 79, the input of the system bus driver 74 is electrically coupled to its output, thereby transferring data at the output of the memory element 72 to the system bus 25 or , Separated from its output. When system bus driver enable 79 separates the input and output of system bus driver 74, system bus driver 74 imparts high impedance to system bus 25. The system bus enable 79 is also generated by the clock decoder 63 in accordance with a clock signal received from the system bus 25 and a control signal received from the node specific logic 65.

The memory element 80 has an input terminal connected to the system bus 25 and an output terminal connected to the input of the node bus driver 82. The output of the nodebus driver 82 is connected back to the nodebus 67. The memory element 80, which is preferably a transparent latch, is controlled by a system bus latch control signal 85 derived from a timing signal generated by the clock decoder 63. The node bus drive signal 87 controls the node bus driver 82 in the same manner as the system bus drive signal 79 controls the system bus driver 74. Thus, in response to the nodebus drive signal 87, the nodebus driver 82 couples its input to its output or separates its input from its output, and high impedance to the node bus 67. To supply.

In order to explain how data is transmitted over the system bus 25, it is important to understand the relationship between the system bus drive enable 79 and the control signal 85. In this embodiment, this relationship is shown in FIG. The system bus drive enable 79 is drawn from the start of the bus cycle to the end. The new data becomes valid for reception from the system bus 25 at some later time in the bus cycle after driver propagation and bus settling times have occurred. In this embodiment, the memory device 80 is a transparent latch. The control signal 85 is logically identical to the clock C45. Bus timing ensures that system bus 25 data is valid for occasional reception prior to the deassertion of control signal 85. The memory device 80 stores bus data that is stable at least at the setup time before deassertion of the control signal 85 and remains stable for a hold time after deassertion of the control signal 85.

The node bus 67 is preferably a very high speed data bus that allows bi-directional data transfer between the node specific logic 65 and the system bus 25 by the data interface 61. In the preferred embodiment of node 60 shown in FIG. 2, nodebus 67 is a dual user system consisting of a point-to-point connection between system bus interface 64 and node specific logic 65. However, according to the present invention, there is no requirement that such connections and the nodebus 67 support two or more cycles.

5 shows a preferred embodiment of a central arbiter 28 also connected to the system bus 25. The central arbiter 28 supplies a clock signal to the system bus 25 and grants ownership of the bus to the node on the system bus 25. The central arbiter 28 preferably includes an arbitration circuit 90, a clock circuit 95 and an oscillator 97. Oscillator 97 generates a basic clock signal. The clock 95 supplies timing signals for the arbitration circuit 71 and supplies basic time H, time L, and phase clock signals for timing on the system bus 25. The arbitration circuit 71 receives the commander and responder request signals, arbitrates the conflict between nodes that require access to the system bus 25, and dequeues the queue mentioned above for the commander and responder requests. Keep it. The arbitration circuit 71 also supplies certain control signals to the clock 95.

B. Interlock Operation Description

As briefly described above, many different types of transactions are allowed on the bus 25. In each case, a transaction consists of one or more separate transfers from one node to another. When the responder node successfully receives a command transmission for one or more bus cycles, it generates an acknowledgment at the beginning of the second bus cycle after each cycle of transmission. Such acknowledgment signals do not indicate successful execution of the commands originally included in the transmission, but merely indicate that the transmission was successfully loaded on the input queue at a given responder node. Transactions related to the present invention will be briefly described below.

A read transaction is used to move data from a specific location in the responder node that manages the address space area for the commander node into a 4, 8, 16, or 32 byte block. In a preferred embodiment, memory and I / O operations are related to a common address space. The responder node may be a memory node, a processor node, or an I / O node.

Interlock read transactions are similar to read transactions. However, the exact effect of the interlock read transaction depends on the lock tag state at the responder node in the manner described in detail below. The lock tag prevents access to a location or group of locations in the address space. The effect of the lock tag can be understood by showing the address space of the system 20 as it appears on a metal "blackboard". The lock tag behaves like a magnetic tag that is removably placed on top of a location or group of locations on the address space “black board”. If the position in the address space specified in the interlock read transaction is already covered with a lock tag, i.e. when that particular address space is blocked, the responder node responds to the interlock read request with a blocked response message and returns. There is no data. This indicates to the commander that the location in the address space specified for the interlock read command is not accessible. This locked response message is sent to the commander after the responder node has serviced the interlock read command, and the responder node can then gain access to the bus 25. Thus, the commander receives a response message that is locked at a non-specific time after command transmission of the interlock read transaction.

If the specific position is not locked, i.e., not associated with the lock tag, the information stored at the address specified in the interlock read command is returned in the response message to the command node that issued the interlock read command. The responder node also attaches a lock tag at a location in the address space specified in the interlock read command to deny access to a specific location in the address space for subsequent interlock read commands.

The unlock write transaction is a complementary relationship to the interlock read transaction. If the command node successfully completes the read and modify position in a read-modify-write operation, it must unlock the position in the address space temporarily locked by the interlock read command. The commander accomplishes this operation by performing an unlock write transaction for a particular location in the address space to properly write modification data into the particular location. The responder node processes the unlock write command by unlocking the address space and writing the required data. The lock tag is then cleaned in the manner described in detail.

The message sent over the bus 25 during the interlock read command transmission contains data on the 64 data lines. The data is a 4-bit instruction field, for example a 2-bit length field specifying the number of words transferred from memory 39 to processor node 31, and an address in memory 39 where data is required to be read. It contains a 30-bit address field that specifies the location. Another line of the system bus 25 that carries information during the interlock read command is a four function line that conveys a 4-bit function code indicating a command transfer, and a six-bit code that identifies the commander node that initiated the interlock read command. 6 ID lines and 3 parity lines.

As briefly described above, system bus 25 includes a response signal used by the transmitter to indicate successful reception of information carried on the bus by the transmitter. In a preferred embodiment, the response signal includes three identical wired OR confirmation (CNF) lines. Three lines are provided especially for writes to interlock commands or I / O registers, since it is very important for the integrity of the bus transaction that the commander knows exactly what the responder did in response to each command. Thus, the receiver will transmit an acknowledgment (ACK) by asserting all three CNF lines or a NACK signal by not asserting all three CNF lines. If all three CNF lines are not received by the receiver at the same logic level, an error correction logic is configured in the receiver to determine the true CNF state.

The ACK acknowledgment indicates that the responder has accepted information from one command transmission cycle or that the commander has accepted information from one response message cycle. The read command transfer cycle that generated the ACK acknowledgment indicates that the responder returned the read response message at some later time.

The NACK acknowledgment returned on the CNF line indicates that the receiver did not allow information from the bus cycle of command transmission. This can be caused by three reasons: (1) A parity error has occurred on the system bus 25. (2) The receiver cannot temporarily accept commands, for example when the receiver's input queue is full. (3) There is no responder node corresponding to a particular address.

The acknowledgment corresponding to the bus cycle is carried on the CNF line by the receiver node at the beginning of the second cycle after the bus cycle.

An embodiment of an interlock read transaction will be described with reference to FIG. The horizontal axis at the top of FIG. 6 represents the continuous bus cycle on the bus 25. The label shown vertically along the left side of FIG. 6 indicates a group of lines included in the bus 25, namely, function lines, data lines, ID lines, confirmation lines and arbitration lines. The entries in the matrix formed by the horizontal and vertical axes of FIG. 6 describe the data types that appear on a particular busline during a particular bus cycle.

In bus cycle 0, the first commander node, e.g., node 31 in FIG. 1, is assigned to the arbiter 28 as one of its CMD REQ arbitration request lines (point-to-point line connected to the arbitrator 28). Assess (shown in Figure 1).

Thus, FIG. 6 shows the " cmdr # 1 " request present on the arbitration line of the system bus 25 in cycle 1. FIG. If other nodes of higher priority are not simultaneously requesting access to the bus, processor 31 obtains bus access in cycle 1 and sends a message to system bus 25.

The information on the function line of the bus 25 during cycle 1 indicates that the information on the bus is command (cmd) information. The data carried on the data line of bus 25 is an interlock read transaction, with instructions and address (c / a) data identifying the current transaction and specifying an address in memory 39 where the data is returned to processor 31. Is done. During bus cycle 1, the ID line contains the identification code of the processor (command / cmdr) node 31 currently transmitting on the bus 25.

During bus cycle 2, there is no information on bus 25 associated with the current interlock read transaction.

At the beginning of bus cycle 3, which is two cycles after the start of the interlock read transaction, i. The memory 39 then places a command message in its input queue.

At the end of bus cycle 3, the first transfer in the interlock read transaction ends. Due to the pending nature of the transaction on the bus 25, the time at which the requested information is returned from the memory 39 to the processor 31 is not exactly defined. The response time depends on the length of time required by the memory 39 to process the request information and the amount of time required on the system bus to handle the additional traffic on the bus 25 generated by another node. The non-specific nature of the time between two transmissions of an interlock read transaction is indicated by the dashed line between bus cycles 3 and 4 in FIG. Thus, although subsequent information occurring via buscycles 4 to 7 is indicated by FIG. 6, this is merely a specific implementation of the timing involved in an interlock read transaction and the second transmission of such a transaction is any subsequent cycle of bus 25. You should know that this can happen in.

The memory 39 processes the interlock read command by removing the interlock read transfer message from its input queue and checking the address information included in the transfer. The information is compared to the address value stored in the lock tag to explain more fully. If the stored address value of the interlock read transfer coincides with the address information, this indicates that the predetermined address position has been locked by the previous interlock read command. The memory 39 then generates a locked response message in the output queue of the memory node 39 that includes the block function code along with other information required for the response message.

When the comparison of the address value stored in the lock tag with the interlock read transfer address information does not produce a "hit", that is, when the transmitted address does not correspond to any stored address, the memory node 39 is connected to the function line. A response message consisting of a valid read response node, such as a "good read data" (grdo) for the < RTI ID = 0.0 >, < / RTI > the contents of a particular address location for the data line, and the commander identification code of the commander node that initiated the interlock read command for the ID line. Configure This response message is loaded into the output queue of the memory node 39.

When memory 39 has processed an interlock read transaction and generated a response message in its output queue in a manner that will be described more fully, memory 39 is directed to the RES REQ request line for arbitrator 28 (shown in FIG. 1). Assert another point-to-point line. Thus, the arbitration line carries a responder request indication as shown in Figure 6 in bus cycle 4. At this time, assuming that no other node has a higher priority, the arbiter 28 allows the memory 39 to access the bus 25 during bus cycle 5. The memory 39 sends a response message containing a " good read data " grdo signal to the function line of the system bus 25, and the memory specified by the address field of the initial transfer from the processor 31 to it. Transfers 8 bytes (i.e., 64-bit) data from the location through the data line of the system bus 25, and combines the return data with the commander, i.e., the processor 31, that originally issued the interlock read request. The ID of the processor 31 is transmitted to the ID line.

During bus cycle 6, the traffic associated with this interlock read transaction does not appear on the system bus 25. Finally, the interlock read transaction is terminated in bus cycle 7 when the processor 31 sends an ACK acknowledgment to the acknowledgment line of the bus 25.

The second read transaction for the same specific location in memory will cause the data to appear on the bus as shown in cycles 8-15 of FIG. In cycle 8, the second commander Cmdr # 2 initiates a commander request for the arbiter 28. Bus cycles 9-12 generate the same amount of traffic on bus 25 as cycles 1-4. However, in the processing of the received interlock read command, the memory 39 finds a match between the address value stored in the lock tag and the address transmitted in the interlock read command. Thus, for example, there is a LOC response on the functional line of bus 25 in cycle 13. Bus cycles 14 and 15 are identical to cycles 6 and 7.

C. Description of Processor 31

Referring to FIG. 7, a more detailed block diagram of the node specification logic 65 in the processor 31 is shown. Processor node 31 includes bus interface circuit 64 as all nodes do. Processor node 31 also includes processor logic 202. As shown in FIG. 7, processor logic 202 includes a central processing unit (CPU) circuitry necessary to execute software in a manner well known to those skilled in the art. The processor logic 202 also generates command and address information as required by the system 20 to perform the necessary application functions as well as to control transmission over the system bus 25.

In addition, the processor node 31 performs parity check on the signals, functions, data, ID, and parity lines of the system bus 25 received from the bus interface circuit 64 in a manner known in the art. And a parity error check circuit 204 for monitoring. The detected parity error will generate a parity error indication on signal line 206.

The information on the ID line is monitored by the comparator circuit 207, which includes the comparator circuit 207 of the processor 31 from the hardwired connection 210 on the backplane, determined by the position of the processor 31 in the mounting cabinet. An identification code is also supplied. The comparison result from the comparator 207 is supplied to the recognition confirmation generator 208 together with the information on the parity error signal line 206.

If no parity error is detected and the ID code received via the bus 25 for the response message matches the ID code of the processor 31, a second bus cycle after each cycle of response transmission directed to the processor 31 Initially, the acknowledgment indication generator 208 sends an ACK acknowledgment via the CNF line of the bus 25.

The function of the bus 25 and the information on the data lines are supplied to the response decoder 212 via the bus interface 64. Decoder 212 is enabled by comparator 207 when a message over bus 25 is intended for processor 31. This is determined by the comparison result from the comparator 207. When the decoder 212 is enabled by the comparator 207, the decoder 212 extracts the function code from the function lines of the system bus 25 and, in the case of any function code, the bus 25 for proper behavior. Command and data information from the line ()) are supplied to the processor logic unit 202.

When processor 31 wishes to initiate a transaction on bus 25, command, address and data information is supplied to command generator 214 along with this node's ID supplied from connection 210. The command generator 214 prepares the command transmission message and instructs the arbiter 28 (not shown in FIG. 7) that the processor 31 requires access to the bus 25 to send the command message. Assess node CMD REQ mediation line 216 to do so. Using an arbitration system, the arbiter 28 allows bus access to the processor 31 at non-specific times after the original interlock read transfer.

If access is granted, command generator 214 causes bus interface 64 to send a command message from command generator 214 to system bus 25.

The responder node to which the interlock read command is directed generates an acknowledgment for two cycles after the transmission of the interlock read command. In particular, as shown in FIG. 7), the command generator 214 acknowledges the ACK on the CNF busline for exactly two bus cycles after each cycle of command transfer is sent by the processor 31 over the system bus 25. Monitor CNF lines to detect presence.

Due to the presence detection failure of the ACK acknowledgment, in the preferred embodiment, an appropriate corrective action is made by retransmission of the previous command. When the transmission ends, the responder node processes the interlock read command and returns a response message on the system bus 25. Due to the uncertainty due to the traffic volume and queue length on the system bus 25, the responder node will generate a response message at non-specific times after sending the command.

D. Description of Memory 39

8 shows a block diagram of a memory 39 that can function as a responder node. As can be seen in FIG. 8, memory 39 includes instruction decode and address and parity check circuit 300. The circuit 300 is connected to the bus function, address and ID lines, and performs parity check in a known manner. The circuit 300 also compares the information on the bus address lines with the limits of the address space provided by the memory 39 when supplied from the register 302 and supplies the comparison result on the address load line 301. . If the address information received via the bus 25 is in the address space area provided by the memory 39 and no parity error has occurred, then the recognition generator 304 connected to the circuit 300 is connected to the memory 39. An ACK acknowledgment is generated by asserting all three CNF lines at the beginning of the second cycle after the directed transmission cycle.

According to the invention, the memory comprises means for receiving an interlock read command from the commander node. Preferably, the memory comprises means for sending an acknowledgment to the node of the commander at a predetermined time subsequent to the initiation of the interlock read command. Also preferably, the means comprises recognition means for sending a recognition instruction to the processor node after a predetermined number of bus cycles following the command message. As implemented herein, such means includes a CNF line into bus interface 64, input queue 306, circuit 300, address register circuit 302, recognition indication generator 304, and memory 39. Equipped. Input queue 306 causes messages received via bus 25 at high speed to be stored until such messages are made due to the relatively slow logic of memory 39. The input queue 306 is enabled to store a message from the bus 25 when the address information appearing in the message on the bus 25 is within the address space limit for the memory 39, which is an address match signal 301. Is determined by

According to the invention, the memory has command decoder means for removing a stored message from an input queue and generating interlock read and unlock write commands and address data from the message. As implemented herein, such means includes a decoder 308. The output of the input queue 306 is supplied to the decoder 308, which extracts address and command information from the messages stored in the input queue 306. Although the decoder 308 supplies multiple instructions to decode several commands and supplies address information on a series of parallel signal lines, the decoder and the output of the decoder 308 and the output of the commands are shown in FIG. Are shown respectively.

According to the present invention, the memory 39 includes storage means for storing information. As implemented herein, the storage means includes a memory array 312. As is known in the art, information is stored in a plurality of discrete locations in the memory array 312 identified by an address that can be specified with read and write instructions supplied to the array 312.

According to the invention, the memory 39 comprises lock means coupled with the storage means and operable between an unlocked state and a locked state, the lock means allowing access to the storage means in the unlocked state and storing means in the locked state. Means to deny access to a. Preferably, the lock means comprises a lock controller means which, in response to the interlock read command and address data from the decoder means, interlocks in the lock memory register if the interlock read address is not already present in the lock memory register. The read address data is placed, the memory array address position corresponding to the data stored in the lock storage register is placed in the locked state, and the unlock writing stored in the lock storage register is performed in response to the unlock write control from the decoder means and the address data. The memory array address position corresponding to the data is positioned in the unlock state, and in response to the interlock read control data, a lock state signal corresponding to the memory array address position state specified by the interlock read address data is generated. Preferably, the lock controller means has means for restoring the memory array address location for the unlock state if the response message is not successfully received by the processor node. As implemented herein, such means includes a lock controller 310.

The invention also includes command means, which in response to an interlock read command from one of the processor nodes, generate a lock state indication indicative of the state of the lock means and switch the lock means from an unlocked state to a locked state. And in response to the unlock write command, store the modified information in a specific position and switch the lock means from the locked state to the unlocked state. As implemented herein, the command means comprises a lock controller 310 and a memory array 312.

Address and command information is supplied to the lock controller 310 which performs the locking structure which will be described in detail later. In addition, address and command information from the decoder 308 are supplied to the memory array 312. The memory array 312 reads / writes data to locations in the array 312 specified by address information received from the decoder 308 in response to read and write commands.

According to the present invention, the memory 39 comprises status response means for transmitting a lock status message including a lock status indication to the processor node that issued the interlock read command at a non-specific time following the initiation of the interlock read command. do. Preferably, the response generator is adapted to generate a first message form containing the content of a particular position when there is a lock means in the unlocked state and a second message form indicating the uselessness of that particular position when the lock means is in the locked state. A response means is provided. As implemented herein, the status response means has a response generator 316 and an output queue 318.

The lock status signal 314 from the controller 310 and the memory data from the memory array 312 are supplied to a response generator 316 which generates an output response message which will be described in detail later. The response message from the generator 312 is supplied to the output queue 318 for storage until the memory 39 gains access to the bus through the arbitration process described above.

The response generator 316 prepares a response message according to the data received from the 312, the lock status signal 314 received from the controller 310, and the command and ID information received from the decoder 308. The response message prepared by the generator 316 is one of two forms depending on whether the memory 39 is allowed to supply the requested data. If the command being answered is a non-interlock read command, or if the command is an interlock read command and the lock status signal 314 is not asserted, then the response generator 316 may request the requested contents of a particular location in the memory 312. Prepare a message of the first type to include. However, if the command is an interlock read command and the lock status line 314 is asserted, the response generator 316 may indicate that a particular address of the interlock read command is in the locked state and that the requested data is responsive to the received interlock read command. To prepare a message of the second type with a block code on the function line indicating that it is not configured in the response message sent by the memory 39.

According to the present invention, the memory 39 obtains access to the bus 25 for storing the response message from the response generator 316 and at a non-specific time following the initiation of the corresponding instruction by the processor 31. And output queue means for transmitting the response message stored to the processor node 31 afterwards. As implemented herein, such means includes an output queue 318. When generator 316 has compiled a response message, it is supplied to output queue 318. The output queue 318 signals the bus interface 64 that the memory 39 requires access to the bus 25. The response message is stored in the output queue 318 for a non-specific time until such access is obtained.

When the memory 39 is allowed access to the bus 25, the response message contained in the output queue 318 is loaded on the system bus 25 for transmission to the commander node that originally issued the command. It is not known when the memory 39 will terminate execution of the command originally sent by the commander node, and also when the memory 39 will gain access to the bus 25 to supply the requested data or lock status information. As this is uncertain, the lock status information corresponding to the interlock read command appears on the functional line of the bus 25 at the commander node at a non-specific time following the initiation of the original interlock read command.

If the commander node does not receive a response message generated by the responder node after a successful interlock read command, the commander node does not issue a recognition indication. If the responder node does not receive or acknowledge the acknowledgment from the response message, it clears the lock bit set by the interlock read command.

According to the invention, the memory 39 comprises means for selectively generating first and second types of response messages, wherein the data messages of the first manner are adapted to store information stored when the locking means is in the unlocked state. And a second type of data message indicates the uselessness of the information when the locking means is in the locked state. As implemented herein, such means includes a lock status line 314, a response generator 316, a decoder 308, and a lock controller 310.

E. Description of Lock Controller 310

Referring to FIG. 9, a more detailed block diagram of the lock controller 310 is shown. According to the invention, the lock means comprises lock tag means for receiving the selected address corresponding to the address in the memory array 39 in which the interlock read command is prevented. As implemented herein, the lock tag means comprises logical controllers 352b, 352c, and 352d that together with the logic controller 350 make up the lock controller 310. It should be noted that more or fewer lock tags can be configured depending on the particular application. The lock tags 352a-d are identical in configuration and operation. For clarity, a detailed circuit is shown only for the lock tag 352a.

Each lock tag 352a-d includes a storage register 354 for storing a value corresponding to a position in the address space of the system 20. The register 354 includes an output terminal 356 that shows the value stored in it. The register 354 also includes an input terminal 360 and an enable terminal 358 connected to the address line 309. Operating the enable terminal 358 causes the register 354 to load the signal carried on the address line 309.

The register output terminal 356 is connected to one input terminal 366 of the comparator 368. Comparator 368 has another input terminal 370 connected to address line 309. The output terminal 372 of the comparator 368 constitutes a " matching " signal supplied to one input terminal of the two-input AND gate 374. The other input terminal of the AND gate 374 is connected to the unlock writing line 380 of the command line 311. The output terminal of the AND gate 374 is connected to the reset terminal of the latch 382.

The output terminal of the latch 382 constitutes a block signal supplied to one input terminal 387 of the two-input AND gate 386. The AND gate 386 and the other input terminal are connected to the match signal output of the comparator 368. The output of the AND gate 386 constitutes a "hit" signal indicating that the address appearing on the address line is blocked by the lock tag 352.

The final component of the lock tag 352a is a four input AND gate 388. One input of the AND gate 388 is connected to a line 390 of the command line 311 indicating that the command currently being processed by the memory node 39 is an interlock read command. The second input of AND gate 388 is connected to clock signal 389 to properly gate the operation of lock tag 352a and prevent race conditions. The third input of the AND gate 388 is connected to the "assignment" terminal of the logic controller 350 to be described below. The fourth input terminal of the AND gate 388 is connected to the inverted lock state signal 314. The output terminal of the AND gate 388 is connected to the enable input 358 of the register 354 and the set terminal of the latch 382.

The logic controller 350 includes a lock tag assignment circuit 392 that functions as a selection encoder for selecting an idle lock tag. The assignment circuit 392 determines that the lock tag is in the free state by the state of the lock bits from the lock tags 352a-d, and is effective for providing a locking function by generating a "assign" signal for the selected lock tag. Assign one of the lock tags.

When all of the lock tags are currently assigned, all non-cleared output signals are supplied to one input of the five input OR gate 394. The other inputs of the OR gate 394 are supplied with the respective "hit" signals of the lock tags 352a-d.

The operation of the lock controller 310 to process the interlock read command will now be described. The address value on the address line 309 is constantly compared with the address value stored in the register 354. If none of the address values stored in the register 354 is the same as the address value appearing on the address line 309, the match signal is not asserted and the "hit" signal is not asserted. Assuming that neither of the circuits 392's busy signal is also asserted, the input of the OR gate 394 is not active and the lock state line 314 is not set. The memory array 312 (FIG. 8) then supplies the contents of the particular location to the response generator 316. The non-assertion of the lock status line 314 causes the response generator 316 to generate a response message of the first type, in which the " good read data " code is set in the response message bit, This response message bit is sent via the function line of the bus 25 to the command code which requested it.

The inverted value of lock status line 314 is now supplied to AND gate 388. Circuit 392 supplies one of the assignment signals of lock tags 352a-d. Since the interlock read is being processed, the interlock read line 390 is set by the decoder 308 (Fig. 8). Thus, when clock signal 389 is activated, AND gate 388 of lock tag 352a is activated to enable register 354. The address value appearing on the address line 309 is stored in the register 354 of the lock tag 352a. In addition, the latch 382 is set due to the activation of the AND gate 388 to assert the lock bit of the terminal 384 of the lock tag 352. Access to a specific location contained within register 354 of lock tag 352 is now negated with a subsequent interlock read command.

Subsequent interlock read commands for the locked position produce the following operation. The address value appearing on the address line 309 is the same as the value stored in the register 354 of the lock tag 352a. The match signal at terminal 372 of lock tag 352a is thus set. Since the lock bit at terminal 384 for lock tag 352a is set from a previous interlock read operation, both inputs of AND gate 386 are now active, causing the hit signal of lock tag 352a to be asserted. This also activates the OR gate 394 to activate the lock status line 314. The activation of the lock status line 314 causes the response generator 316 (FIG. 8) to generate a second type of response message, in which the locked response code is set on the function bits of the message.

The operation of the unlock write command to clear the lock bit will now be described. The unlock write command for the previously locked position causes the same value as the value stored in the register 354 of the lock tag to be loaded on the address line 309. For example, assume that an unlock write command has been sent to unlock the position locked by the lock tag 352a. When an address value appears on address line 309, the output of comparator 368 sets the match signal. Since the unlock write line 391 is also high at this time, the AND gate 374 is activated so that the latch 382 resets the lock bit signal at the output terminal 384. The AND gate 386 is deactivated to remove the active hit signal for the lock tag 352 from the input terminal of the OR gate 394. The data transferred by the unlock write command is then written to a specific location in the memory.

By providing the lock status message supplied to the processor as a data transfer over the system bus at an unspecified time after an interlock read command, the present invention separates the transfer recognition and lock state transfer functions, so that the lock state information can be stored for a predetermined time or dedicated lock state. Provides for the use of multiple lock bits without the necessary cost and complexity when required to be transmitted over the lines. The present invention also obtains lock status information from nodes connected to the system via buses and adapters separate from the system bus.

Throughout the above description, the locked memory, that is, the address space, has been described as " position ". Each address stored in a register may constitute an area of addresses such that a single interlock read command or an unlock write command can lock and unlock areas of positions in an address, respectively, and not lock and unlock only a single position.

It will be apparent to those skilled in the art that various modifications and changes can be made in the bus interface circuit and the interface of the present invention without departing from the spirit and scope of the invention. The appended claims contain such modifications and variations.

Claims (7)

An apparatus for executing an exclusive read-modify-write operation on a fenced bus, the operation comprising: an interlock read command for retrieving information stored at a specific location and for limiting access to the stored information by a subsequent interlock read command; Means for receiving an interlock read command from the commander node, having a series of different transactions on the pending bus including an unlock write command for storing information at the particular location and restoring access to the stored information. and; Storage means for storing information, said specific position being included; Lock means associated with the storage means and operable between an unlocked state and a locked state, the lock means for allowing access to the storage means in the unlocked state and denying access to the storage means in the locked state; In response to the interlock read command, generate a lock state indication indicative of the state of the lock means, switch the lock means from the unlock state to the lock state, and in response to the unlock write command, modify the information modified at the specific position. Command means for storing and switching said lock means from a locked state to an unlocked state; And status response means for transmitting a lock status message corresponding to the lock means status to a non-specified time subsequent to the initiation of the interlock read command to the commander node that has issued the interlock read command. Exclusive read-modify-write operation executor on the bus. 2. The apparatus of claim 1, comprising means for transmitting an acknowledgment signal indicative of receipt of the interlock read command to the commander node at a predetermined time subsequent to the initiation of the interlock read command. 2. The apparatus according to claim 1, wherein said status response means comprises means for selectively generating first and second types of response messages, wherein said first type of data message is adapted when said lock means is in said unlocked state. An information message of a second type, said stored information being inoperative when said lock means is in said locked state. An apparatus for executing an exclusive read-modify-write operation from a processor node on a fenced bus that propagates data during repeated bus cycles, wherein the operation retrieves information stored at a specific location within the memory node and subsequent interlock read instructions. An interlock read command for setting the specific position in the locked state to limit access to the stored information by means of an unlocked state for storing information in the specific position and restoring access to the stored information. Having a series of different transactions on the pending bus including an unlock write command to set the specific location, the transactions being performed via command and response messages sent over the bus, a predetermined number following the command message. Recognize the processor node after a bus cycle of Recognition means for transmitting a time signal; Input queue means for receiving the interlock read command message and unlock write command message from the processor node; Command decoder means for removing a stored command from said input queue means and generating interlock read and unlock write control and address data from said command; A memory array having a plurality of address positions including said specific position, for storing and retrieving said information in response to control and address data from said decoder means; A lock memory register having a position for storing a memory address value corresponding to an address position in the memory array; In response to the interlock read command and address data from the decoder means, if the interlock read address does not already appear in the lock storage register, locate the interlock read address data in the lock storage register and store in the lock storage register. The memory array address position corresponding to the data set in the locked state is set, and in response to the unlock write control and address data from the decoder means, the memory array address position corresponding to the unlock write data stored in the lock memory register. Is set to the unlocked state, and in response to the interlock read control data, a lock controller means for generating a lock state signal corresponding to the state of the memory array address position specified by the interlock read address data. .; In response to the lock status signal, when the specific address is in the unlocked state, a response message is generated that includes the contents of the memory address specified by the address data of the command retrieved from the input queue, and the specific address is in the locked state. Generator means for generating a response message, if present, comprising a locked response; An output queue for storing a response message from the generator means and for obtaining access to the bus at a non-specific time subsequent to the initiation of a corresponding command by the processor node and for transmitting the stored response message to the processor node. Means for executing an exclusive read-modify-write operation from a processor node on a fenced bus for propagating data during a repeating bus cycle. 5. The apparatus of claim 4, wherein the lock controller means comprises means for restoring the memory array address location in an unlocked state if the response message is not successfully received by the processor node. A method for responding to an exclusive read-modify-write operation on a fenced bus, wherein the operation retrieves information stored at a specific location and an interlock read command for restricting access to the stored information by a subsequent interlock read command. And a series of different transactions on the pending bus including an unlock write command for storing information at the specific location and restoring access to the stored information, the method comprising the steps of: receiving an interlock command from the commander node; ; Checking the lock indicator and switching the lock indicator from an unlocked state to a locked state if the lock indicator is in an unlocked state; Transmitting a lock state signal corresponding to the lock indicator state to the commander node at a non-specific time subsequent to the initiation of the interlock read command; Storing modified information at said specific location and switching said lock indicator from unlocked state to unlocked state upon receipt of an unlock write command; and responding to an exclusive read-modify-write operation on a fenced bus. How to. 7. The method of claim 6, further comprising transmitting an acknowledgment signal indicative of receipt of the interlock read command to the commander node at a predetermined time subsequent to the commencement of the command.

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