JP2001154979A - Bus bridge device, computer system and bus cycle control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency by dynamically changing the kinds of cycles generated on another bus in accordance with the contents of a memory reading cycle generated on one bus. SOLUTION: A single/burst judging circuit 141 judges whether the memory reading cycle is a single cycle or a burst cycle when an address designated by the memory reading cycle on a secondary PCI bus 3 belongs to a pre-fetching possible address range. When the single one is judged, a bus cycle for pre- fetching is not executed. The bus cycle for pre-fetching is executed on a primary PCI bus 2 only when the burst cycle is judged. Thus, a trouble that a useless pre-fetching cycle is executed is eliminated so that data transfer efficiency is improved in a whole system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus bridge device, a computer system using the same, and a bus cycle control method, and more particularly to a bus bridge device having a prefetch function, a computer system using the same, and a bus cycle control method.

[0002]

2. Description of the Related Art Generally, personal computers (P
C) or a PC server, a PC (Peripherer) is used as a system bus.
al Component Interconnect
t) A bus is used.

In the PCI bus, data transfer is based on block transfer, and each block transfer is realized by using burst transfer. Thereby, for example, PC
133 Mbytes / sec on I bus (32 data buses)
(At the time of bit width).

[0004] In the PCI bus specification, in a memory read cycle (memory read, memory read line, memory read multiple), when a specified address is within a prefetchable (prefetchable) range, a master transfers data. Subsequent data can be prefetched to increase efficiency. This prefetch function is a PCI bus for connecting between two PCI buses.
-Also applies to PCI bridges.

That is, when the master that issues a memory read cycle and the target of that cycle are on different buses, the PCI-PCI bridge sets the bus cycle generated on one PCI bus to a memory read, and If the address is within the prefetchable range, a bus cycle for continuously reading the data of that address and the data of the address following it from the memory is output on the other PCI bus. This allows
Data can be prefetched from the memory on the other PCI bus to the PCI-PCI bridge.

[0006]

However, in practice, the PC
Since the I-PCI bridge itself does not use memory data, prefetching may be performed on a memory area not intended by the master that first generated the memory read cycle.

In other words, if the master that first generated the memory read cycle needed only one transfer cycle of data (4 bytes or less), a wasteful prefetch cycle was generated by the PCI-PCI bridge. This causes the data transfer efficiency of the entire system to decrease.

The present invention has been made in view of the above circumstances, and the type of a cycle generated on the other bus can be dynamically changed in accordance with the content of a memory read cycle generated on one bus. Thus, an object of the present invention is to provide a bus bridge device, a computer system, and a bus cycle control method capable of improving data transfer efficiency.

[0009]

According to the present invention, there is provided a bus bridge device for connecting between a first bus and a second bus, wherein the bus cycle on the first bus is the same as that of the first embodiment. Bus cycle execution means for issuing a bus cycle on the second bus based on a bus cycle on the first bus so as to be transmitted on a second bus;
If the address specified by the memory read cycle on the first bus belongs to a prefetchable address range in the memory space on the second bus, the memory read cycle on the first bus is performed once. And a single / burst determining means for determining which cycle is a single cycle terminated by the data transfer cycle or a burst cycle including a plurality of data transfer cycles. When the memory read cycle is determined to be the burst cycle by the burst determination means, the memory at the address subsequent to the address specified by the memory read cycle is prefetched into the bus bridge device. The data at the address specified in the read cycle and its data The second the first bus cycle for reading continuously the data of the subsequent addresses
When the memory read cycle is determined to be the single cycle by the single / burst determination means, a second data for reading data at an address designated by the memory read cycle is issued.
Is issued on the second bus.

In this bus bridge device, when an address specified by a memory read cycle on the first bus belongs to an address range that can be prefetched, the memory read cycle ends with one data transfer cycle. It is determined whether the cycle is a single cycle to be performed or a burst cycle including a plurality of data transfer cycles. If it is determined that it is a single cycle,
A bus cycle for prefetch is not executed, and only when it is determined that the cycle is a burst cycle,
A bus cycle for prefetch is executed. This eliminates the problem that a useless prefetch cycle is executed, and improves the data transfer efficiency of the entire system.

In the single / burst determination, a frame signal indicating the start and period of a bus cycle on the first bus is monitored, and the frame signal at the next clock timing of the address phase is either deasserted or asserted. You can do this by checking.

If it is detected from the command specified in the address phase that the memory read cycle on the first bus is a memory read line or a memory read multiple, a single / burst of the memory read cycle is detected. , It is preferable to execute a bus cycle for prefetch uniquely.
This is because the memory read is used for both single / burst, but the memory read line and the memory read multiple are usually used only for the burst transfer.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention. This computer system is a personal computer (PC) or PC
It is used as a server, and as shown, a processor bus 1, a primary PCI bus 2, a secondary PCI bus 3, a CPU 11, a host-PCI bridge device 12, a main memory 13, a PCI-PCI bridge device 1
4 and PCI devices 15, 16, 17 and the like.

The CPU 11 controls the operation of the entire PC system, and executes an operating system, a system BIOS, and various other programs loaded into the main memory 13. The host-PCI bridge device 12 is a bridge device for connecting the CPU bus 1 and the primary PCI bus 2 in two directions, and also includes a memory control logic for controlling access to the main memory 13 and the like. This host-PCI bridge 12 device can function as a bus master on the primary PCI bus 2.

The main memory 13 stores an operating system, an application program / utility to be processed, user data created by an application program, and the like.

The primary PCI bus 2 and the secondary PCI bus 3 include various devices (storage device, display device,
Communication device). The PCI bus is a parallel transmission line including a multi-bit width address / data line and the like. A bus cycle (bus transaction) on the PCI bus basically includes an address phase for command and address output, and a subsequent address phase. And one or more data transfer phases. These two PCs
The PCI-PCI bridge device 14 connects the I buses 2 and 3 and controls transmission of a bus cycle between the PCI buses 2 and 3.

That is, the PCI-PCI bridge device 1
Reference numeral 4 denotes a bidirectional connection between the primary PCI bus 2 and the secondary PCI bus 3, and the CPU 11, the host-PCI bridge 12, and the PCI device 15 on the primary PCI bus 2 are connected to the PCI bus 3. Accessing the above PCI devices 16, 17;
And the PCI devices 16 and 17 on the PCI bus 3 can access the PCI device 15 and the memory 13 on the primary PCI bus 2.

The PCI bus 2 closer to the host as viewed from the PCI-PCI bridge device 14 becomes the primary PCI bus of the PCI-PCI bridge device, and the farther PC
I bus 3 is a secondary P of the PCI-PCI bridge device
It becomes a CI bus.

The PCI-PCI bridge device 14 of the present embodiment is provided with a single / burst determination circuit 141 and a prefetch buffer 142 as shown in the figure. The single / burst determination circuit 141 determines that the memory read cycle for the memory 13 generated from the PCI devices 16 and 17 on the secondary PCI bus 3 is 1
This is for determining whether the cycle is a single cycle terminated by one data transfer cycle or a burst cycle including a plurality of data transfer cycles.

If it is determined that the cycle is a burst cycle, the PCI-PCI bridge device 14 sets a burst memory for continuously reading data at an address designated by the memory read cycle and data at an address subsequent thereto. Issue a recycle on primary PCI bus 2. As a result, not only the data at the address specified in the memory read cycle but also the data at the address subsequent thereto are read from the memory 13 and read from the
-Prefetch buffer 1 in PCI bridge device 14
42 is prefetched. On the other hand, if it is determined that the cycle is a single cycle, the PCI-PCI bridge device 14 does not execute the burst cycle for prefetch, but performs the single memo for reading the data at the address specified in the memory read cycle. Issue a recycle on primary PCI bus 2.

Next, a method for determining single / burst will be described with reference to FIG.

In general, when a device on the PCI bus becomes a master and generates a bus cycle, the cycle is controlled mainly by using control signals of a frame signal (FRAME #) and an initiator ready signal (IRDY #). I do. Using this control signal, it is possible to determine whether the master that has generated the cycle intends to end the cycle with only one transfer of data or to perform two or more transfers.

First, the meaning of the signal lines on the PCI bus shown in the timing chart of FIG. 2 will be described.

The frame signal (FRAME #) is
This signal is driven by the master on the bus to indicate the start of access and the period of access. That is, FR
AME # is asserted "L" to indicate that a bus cycle has been started. Data transfer continues while FRAME # is asserted. FRAME #
Is deasserted, indicating that the next data transfer is the last data transfer in the current bus cycle.

Initiator ready signal (IRDY #)
Is a signal indicating that the initiator (master) is ready for data transfer, and is driven by the master in a read cycle to indicate that the master in that cycle is ready to accept data.

The target ready signal (TRDY #) is a signal indicating that a target, which is a device specified in a bus cycle, is ready for data transfer.
In a read cycle, the target is driven by the target to indicate that the target of the cycle is outputting valid data to the AD bus line.

Command / byte enable signal (C / B
E #) is used to specify a bus command and a valid byte lane. The master outputs a bus command in the address phase to specify the type of bus cycle, and in the data phase, specifies a byte lane to be used for data transfer.

AD is a 32-bit bus signal used for transferring addresses and data. In the address phase of a cycle, it is always driven by the master of that cycle. In the data phase, when TRDY # is asserted to "L" in the read cycle, it becomes a valid value and is driven.

Here, the address phase is one clock range after the master asserts FRAME #, and the target on the PCI bus samples an address at the first rising edge of the clock (timing 1). The data phase is a phase following the address phase,
When RDY # and TRDY # are simultaneously in the asserted state “L”, actual data transfer is performed, and FRAME # and IR
When DY # is simultaneously "H", the data phase ends.

FIG. 2A shows a memory read cycle when two data transfers are performed, and FIG.
Indicates a memory read cycle when the cycle is completed by one transfer.

Here, it should be noted that FRAME # always becomes "H" and IRDY # becomes "L" in the final transfer.
In other words, the master sets FRAME # to "H" to notify the target that there is no intention to transfer any more, and the cycle ends after the final transfer is performed.

In particular, as shown in FIG. 2B, if the master of the cycle drives IRDY # to "L" at the same time as driving FRAME # to "H" after the address phase, the master becomes 1 It may be determined that the transfer is to end the cycle, and the target may end the cycle when it has driven one more transfer of data.

The present invention uses this feature to improve data transfer. That is, the single / burst determination circuit 141 of the PCI-PCI bridge device 14
Monitors the FRAME # and IRDY # and checks the states of the FRAME # and IRDY # at the next clock timing (timing 2) of the address phase, so that the memory read cycle issued by the master is one transfer and the cycle ends. Is determined (single cycle) or terminated after two or more data transfers (burst cycle). PC
If the I-PCI bridge 14 terminates the cycle by one transfer even in the same memory read cycle,
Stop prefetching read, primary PCI
A read cycle of only one transfer is output to the bus 2. As a result, useless prefetch reading can be avoided.

Since only one data transfer is performed after FRAME # is deasserted, in principle, even if IRDY # is not monitored, the clock at the next clock timing (timing 2) of the address phase can be used. F
A single / burst determination can be made only by checking the state of the RAME #. The PCI specification states that the master must assert IRDY # after deasserting FRAME # until the last data transfer is completed. Therefore, in practice, it is possible to cope with various operations of the master by performing the single / burst determination in consideration of not only the state of FRAME # but also the state of IRDY # as described above. It becomes.

Next, referring to FIGS. 3 and 4, the PCI-PCI bridge device 14 for realizing the above operation will be described.
Will be described.

The PCI-PCI bridge device 14 is configured as shown in FIG.
, The target control unit 21 and the master control unit 22 used for transmitting the bus cycle from the primary PCI bus 2 to the secondary PCI bus 3, and the bus cycle from the secondary PCI bus 3 to the primary PCI bus 2. A target control unit 31 and a master control unit 32 used for transmission are provided.

From the primary PCI bus 2 to the secondary P
In transmitting a bus cycle to the CI bus 3, the target control unit 21 operates as a target for the master on the primary PCI bus 2. The master control unit 22 transmits the bus cycle from the master on the primary PCI bus 2 to the secondary PCI bus 3
And issues a bus cycle on the secondary PCI bus 3.

Similarly, in transmitting a bus cycle from the secondary PCI bus 3 to the primary PCI bus 2, the target control unit 31
2 as a target for the master above. The master control unit 32 operates as a master of the primary PCI bus 2 to transmit a bus cycle from the master on the secondary PCI bus 32, and
A bus cycle is issued on the CI bus 2. Secondary P
For a memory read cycle for the memory 13 generated from the PCI devices 16 and 17 on the CI bus 3, the target control unit 31 makes a single / burst determination, and based on the determination result, the master control unit 32 Controls permission / prohibition of execution of the prefetch cycle.

As shown in FIG. 4, the target control unit 31 includes the single / burst determination circuit 14 described above.
1, a decoding circuit 201 is provided.

When a cycle is generated by the master on the secondary PCI bus 3 connected to the PCI-PCI bridge device 14, if the target device of this cycle is on the primary PCI bus 2, the target control unit 31 Must respond to this cycle. For this purpose, the decode circuit 201 decodes the address and determines whether or not the memory window or the prefetch window specified by the information in the configuration register 202 hits. The memory information stored in the configuration register 202 indicates a memory range existing on the secondary PCI bus 3 side in the entire memory space in the system, and the other memory ranges are provided on the primary PCI bus 2 side. Will be. The memory information also specifies a prefetchable address range.

The decode circuit 201 also decodes a command of a bus cycle on the secondary PCI bus 3, and determines whether the command of the cycle is a memory read, a memory read line, or a memory read multiple. Here, the memory read is a basic command for a memory read cycle, and can be used in both single and burst transfers. The memory read line is a command used when performing a relatively large number of transfer cycles, and the memory read multiple is a command used when performing a large number of transfer cycles.

The aforementioned single / burst determination circuit 141
The single / burst determination operation by
This command is executed when the command of the memory read cycle on the CI bus 3 is a memory read command and the address specified in the cycle belongs to a prefetchable address range of the memory address space on the primary PCI bus 2. When the command of the memory read cycle on the secondary PCI bus 3 is a memory read line or a memory read multiple, a prefetch cycle is basically executed.

As described above, in this embodiment, the cycle to be output to the primary PCI bus 2 is determined based on the determination results of the decode circuit 201 and the single / burst determination circuit 141, and the result is determined by the master control unit 3.
2 and the cycle is output to the primary PCI bus 2.

Hereinafter, referring to the flowchart of FIG.
Primary PCI executed when a memory read cycle generated on the secondary PCI bus 3 occurs
An operation for determining a cycle to be output to the bus 2 will be described.

When FRAME # is asserted by the master on the secondary PCI bus 3 and a memory read cycle is started (step S11), the address in the address phase is sampled and checked to make the address of the current cycle primary. The decoding circuit 20 determines whether or not it belongs to the memory range on the PCI bus 2 side.
1 (step S12). If the cycle does not belong to the memory range of the primary PCI bus 2 (NO in step S12), the cycle is changed to the primary PCI bus 2
The PCI-PCI bridge device 14 terminates the processing at that time because there is no need to transmit the information to the side.

If it belongs to the memory range on the primary PCI bus 2 side (NO in step S12), the decoding circuit 201 checks the command in the address phase and determines whether the current cycle is a memory read line or a memory read multiple. A determination is made (step S13).
If the current cycle is a memory read line or a memory read multiple (YE in step S13)
S), a memory read cycle (prefetch cycle) for performing continuous transfer is determined as a cycle to be output to the primary PCI bus 2, and the cycle is executed by the master control unit 32 (step S14).

On the other hand, when the current cycle is neither the memory read line nor the memory read multiple (NO in step S13), the decode circuit 201 determines that the command of the current cycle is a memory read and It is determined whether or not the condition that the address specified in the cycle is in the prefetchable memory address range is satisfied (step S15). If this condition is satisfied (YES in step S15), the determination processing by the single / burst determination circuit 141 is started. The single / burst determination circuit 141 outputs the IRDY # signal at the rising edge of the clock following the address phase.
It is determined whether the current cycle is a single transfer or a burst transfer based on whether the assertion of RRAME # and the deassertion of RRAME # occur simultaneously (step S1).
6).

If the assertion of IRDY # and the deassertion of RRAME # occur simultaneously at the rising edge of the clock following the address phase (YE in step S16)
S) A memory read cycle in which only one transfer is performed is determined as a cycle to be output to the primary PCI bus 2, and the cycle is executed by the master control unit 32 (step S17). On the other hand, if the condition of step S16 is not satisfied (N of step S16)
O), a memory read cycle (prefetch cycle) for performing continuous transfer is determined as a cycle to be output to the primary PCI bus 2, and the cycle is executed by the master control unit 32 (step S14).

Next, a specific bus cycle control operation executed by the PCI-PCI bridge device 14 will be described with reference to the timing chart of FIG.

Here, it is assumed that the bus cycle executed by the master on secondary PCI bus 3 is a single transfer that ends with only one transfer. PCI-P
When the current cycle address on the secondary PCI bus 3 belongs to the memory space on the primary PCI bus 2 side, the target control unit 31 of the CI bridge device 14 first asserts the device select signal (DEVSEL #). Responds to the master on the secondary PCI bus 3. DEVSEL # is a response signal from the accessed target and is driven by the accessed target.

Thereafter, the target control unit 31 outputs a stop signal (S) for instructing the suspension of the current bus cycle.
TOP #) to request a retry to the master on the secondary PCI bus 3. The master that has received the retry request determines that the target cannot accept the current cycle, temporarily suspends the current cycle, and executes the same cycle again after a certain period of time.

After requesting a retry to the master on the secondary PCI bus 3, in the case of a normal PCI-PCI bridge, a burst transfer in which data is continuously read from the memory for prefetch is executed. I will. As a result, the primary PCI bus 2 is occupied for a long period by useless data transfer that is not used by the master on the secondary PCI bus 3.

In the PCI-PCI bridge device 14 of this embodiment, a memory read cycle for performing only one transfer is output to the primary PCI bus 2. Only data for one transfer is read from the memory 13 and stored in the prefetch buffer 142. Therefore, the problem that unnecessary prefetch cycles are executed is eliminated, and the data transfer efficiency of the entire system can be improved.

When the memory read cycle is retried by the master on the secondary PCI bus 3, the PCI-
In response, the PCI bridge device 14 immediately returns the data already read from the memory on the primary PCI bus 2 side to the master.

Next, referring to FIG. 7, the PC of this embodiment will be described.
An application example of the I-PCI bridge device 14 will be described.

FIG. 7 shows the PCI-PCI bridge device 14.
Is configured by two physically different controllers 301 and 302. First controller 3
01 is mounted on the host device side where the primary PCI bus 2 is provided, that is, on the personal computer main body side, and the second controller 302 is connected as necessary for expanding the functions of the personal computer main body. Possible extension unit (mounted on the docking station side. Two controllers 30
The data transfer between the devices 1302 is performed by serial transfer via the serial transfer path 400.

That is, when transmitting a bus cycle from the primary PCI bus 2 to the secondary PCI bus 3, the controller 301
Information (address, command, data, byte enable, and other signal information constituting a bus cycle) indicating the state of a number of upper signal lines is converted from parallel data to serial data.
0 is serially transferred to the controller 302.
In the controller 302, the serial data is restored to the parallel data, which is developed on the secondary PCI bus 3 as a bus cycle. Similarly, secondary PC
When transmitting a bus cycle from the I bus 3 to the primary PCI bus 2, the controller 302 uses the controller 302 to display information indicating the state of a number of signal lines on the secondary PCI bus 3 (address, command, data, Byte enable and other signal information) are converted from parallel data to serial data, which is serially transferred to the controller 301 via the serial transfer path 400. In the controller 301, the serial data is restored to parallel data, which is
It is developed on the bus 2 as a bus cycle.

By using such a PCI serial transfer interface, the computer main body and the docking station can be connected with a thin cable including the serial transfer path 400.

In this case, the controller 302 includes the single / burst determination circuit 141 and the decode circuit 201 as shown in FIG.
2. With the provision of the prefetch buffer 142, the primary PCI bus 2 and the serial transfer path 400 are occupied for a long time due to unnecessary memory data prefetch not used by the master on the secondary PCI bus 3 side. Can be prevented from occurring.

As described above, the PCI-PCI bridge device 1
4 does not necessarily need to be constituted by one LSI, but may be constituted by two physically different LSIs.

In the above description of the present embodiment, only the memory read cycle from the master on the secondary PCI bus 3 side to the memory on the primary PCI bus 2 side has been described, but a memory is provided on the secondary PCI bus 3 side. In this case, the same control can be applied to the memory read cycle from the master on the primary PCI bus 23 side to the memory on the secondary PCI bus 3 side.

[0063]

As described above, according to the present invention,
Useless prefetch cycles can be suppressed, and the data transfer efficiency of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a single / single unit used in the system of the embodiment.
5 is a timing chart for explaining the principle of burst determination.

FIG. 3 shows a PCI-P provided in the system of the embodiment.
FIG. 2 is a block diagram showing a configuration of a CI bridge device.

FIG. 4 is a block diagram showing a configuration of a target control unit provided in the PCI-PCI bridge device of FIG. 3;

FIG. 5 shows a PCI-P provided in the system of the embodiment.
9 is a flowchart illustrating a procedure of a bus cycle determination operation executed by the CI bridge device.

FIG. 6 shows a PCI-P provided in the system of the embodiment.
FIG. 4 is a diagram for explaining a bus cycle executed by the CI bridge device.

FIG. 7 shows a PCI-P provided in the system of the embodiment.
FIG. 2 is a diagram illustrating a configuration in a case where a CI bridge device is realized by two controllers.

[Explanation of symbols]

 2 Primary PCI bus 3 Secondary PCI bus 11 CPU 12 Host-PCI bridge 13 Memory 14 PCI-PCI bridge 15, 16, 17 PCI device 141 Single / burst determination circuit 142 Prefetch buffer 31 Target Control unit 32: Master control unit 201: Decode circuit 202: Configuration register

Claims (7)

[Claims] 1. A bus bridge device for connecting between a first bus and a second bus, wherein the first bus is transmitted to the second bus so that a bus cycle on the first bus is transmitted to the second bus. Bus cycle executing means for issuing a bus cycle on the second bus based on a bus cycle on the bus; and an address designated by a memory read cycle on the first bus is a memory on the second bus. In the case where the memory read cycle belongs to a prefetchable address range in the space, the memory read cycle on the first bus is either a single cycle terminated by one data transfer cycle or a burst cycle including a plurality of data transfer cycles. And a single / burst determination unit that determines whether the bus cycle execution unit is a single / burst determination unit. If it is determined that the memory read cycle is the burst cycle, the data at the address subsequent to the address specified in the memory read cycle is prefetched into the bus bridge device so as to be prefetched in the memory read cycle. A first bus cycle for continuously reading data of a specified address and data of an address subsequent thereto is issued on the second bus, and the single / burst determination means determines that the memory read cycle is A bus bridge device for issuing, on the second bus, a second bus cycle for reading data at an address specified in the memory read cycle when it is determined that the cycle is a single cycle. 2. The memory read cycle defines three types of cycles: a memory read, a memory read line, and a memory read multiple. The memory read cycle includes a command designated by a memory read cycle on the first bus. Further comprising means for determining whether the memory read cycle is one of the memory read, the memory read line, and the memory read multiple, based on the memory read cycle. If the read cycle is the memory read line or the memory read multiple, the first bus cycle is issued on the second bus, and the memory read cycle on the first bus is the memory read cycle. In some cases, according to the judgment result of the single / burst judgment means, Bridge apparatus according to claim 1, wherein issuing a first or second bus cycle on said second bus. 3. The memory read cycle includes an address phase and one or more subsequent data phases, and the single / burst determination means indicates a start and a period of a bus cycle on the first bus. Monitoring a frame signal and determining whether a memory read cycle on the first bus is a single cycle or a burst cycle based on a state of the frame signal at a clock timing next to the address phase. The bridge device according to claim 1, wherein 4. A bus bridge device for connecting between a first bus and a second bus, wherein an address specified in the memory read cycle is responsive to a memory read cycle generated on the first bus. Issue a first bus cycle on the second bus for continuously reading the data of the address and the data of the address following the data, and read the data of the address subsequent to the address specified in the memory read cycle. A prefetch means for prefetching in the bus bridge device, wherein the memory read cycle on the first bus is either a single cycle terminated by one data transfer cycle or a burst cycle including a plurality of data transfer cycles. Single / burst determination means for determining whether there is a Means for permitting or inhibiting the operation of the prefetch means based on a result of the determination. 5. A first and second bus, a bus bridge device for connecting the first and second buses, and an address specified in a memory read cycle on the first bus is When belonging to the prefetchable address range in the memory space on the second bus, the memory read cycle on the first bus is divided into a single cycle terminated by one data transfer cycle and a plurality of data transfer cycles. A single / burst determination unit for determining which of the included burst cycles is included; and if the single / burst determination unit determines that the memory read cycle is the burst cycle, the single / burst determination unit is designated by the memory read cycle. The data of the address following the address that has been prefetched is prefetched into the bus bridge device. As described above, the bus bridge device issues, on the second bus, a first bus cycle for continuously reading data at an address designated by the memory read cycle and data at an address subsequent thereto. Means for reading data at an address specified by the memory read cycle into the bus bridge device when the single / burst determination means determines that the memory read cycle is the burst cycle. Means for issuing said bus cycle on said second bus. 6. A first and second bus, a bus bridge device for connecting the first and second buses, and a bus bridge device provided in the bus bridge device and generated on the first bus. Issue a first bus cycle on the second bus for continuously reading data at an address specified in the memory read cycle and data at an address subsequent thereto in response to the read memory read cycle. And
A prefetch means for prefetching data of an address subsequent to an address specified in the memory read cycle into the bus bridge device; and a memory read cycle on the first bus is terminated by one data transfer cycle. Single / burst determination means for determining which cycle is a single cycle or a burst cycle including a plurality of data transfer cycles; and permitting or deactivating the operation of the prefetch means based on a determination result of the single / burst determination means. A computer system comprising: a prohibition unit. 7. A first system provided in a computer system.
And a bus cycle control method for controlling a bus cycle executed on a second bus, wherein an address specified in a memory read cycle on the first bus is a memory space on the second bus. , The memory read cycle on the first bus is either a single cycle terminated by one data transfer cycle or a burst cycle including a plurality of data transfer cycles. A single / burst determination step of determining whether there is a data read; and if the single / burst determination step determines that the memory read cycle is the burst cycle, data of an address subsequent to an address specified in the memory read cycle For connecting between the first and second buses A first bus cycle for continuously reading data of an address specified in the memory read cycle and data of an address subsequent thereto is provided to the bus bridge device so as to be prefetched in the bridge device. Causing the bus bridge device to issue the address specified in the memory read cycle to the bus bridge device when the single / burst determination means determines that the memory read cycle is the burst cycle. Issuing a second bus cycle for reading data on the second bus.