KR910012917A - Word Deinterleave Circuit - Google Patents

Word Deinterleave Circuit Download PDF

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Publication number
KR910012917A
KR910012917A KR1019890018650A KR890018650A KR910012917A KR 910012917 A KR910012917 A KR 910012917A KR 1019890018650 A KR1019890018650 A KR 1019890018650A KR 890018650 A KR890018650 A KR 890018650A KR 910012917 A KR910012917 A KR 910012917A
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KR
South Korea
Prior art keywords
data
clock
word
byte
rams
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Application number
KR1019890018650A
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Korean (ko)
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KR970006015B1 (en
Inventor
이홍순
Original Assignee
이헌조
주식회사 금성사
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Priority to KR89018650A priority Critical patent/KR970006015B1/en
Publication of KR910012917A publication Critical patent/KR910012917A/en
Application granted granted Critical
Publication of KR970006015B1 publication Critical patent/KR970006015B1/en

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Abstract

내용 없음.No content.

Description

워드 디인터리브(Word Deinterleave)회로Word Deinterleave Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

제2도는 데이타의 전송 형태를 나타낸 도면.2 is a diagram showing a form of data transmission.

제3도의 (가)는 제1도내의 256바이트 RAM의 영역 할당도.(A) of FIG. 3 shows the area allocation of 256-byte RAM in FIG.

(나)는 제1도내의 어드레스 발생 ROM에 기억된 내용.(B) shows the contents stored in the address generation ROM in FIG.

Claims (1)

인터리브되어 있는 비트데이타를 워드 데이타로 변환시키기 위한 11비트 쉬프트레지스터(1)와; 상기 11비트 쉬프트레지스터(1)로 부터 출력되는 데이타를 저장시키기 위한 다수개의 256바이트RAM(2-5)과; 상기 다수개의 256바이트 RAM(2-5)의 입,출력을 제어하기 위한 3상태 버퍼(6-9)와; 상기 다수개의 256바이트 RAM(2-5)의 채널별로 할단된 부분에 데이타를 저장할 수 있도록 하는 어드레스를 발생시키는 어드레스 발생 ROM(10)과; 상기 모든 데이타들의 흐름을 조절하기 위한 클럭을 발생시키는 클럭 발생부(11)와; 상기 클럭 발생부(11)의 클럭을 계수하여 소정의 신호를 어드레스 발생ROM(10)에 출력시키는 계수기(12)와; 상기 다수개의 256 바이트 RAM(2-5)으로 부터 디인터리브되어 출력되는 데이타를 채널별로 분리하여 출력시키는 1×4 디 멀티플렉서(13)와; 다수개의 반전기(14-16)를 상호연결 구성하여서 됨을 특징으로 하는 워드 디인터리브(Word Deinterleave) 회로.An 11-bit shift register 1 for converting interleaved bit data into word data; A plurality of 256-byte RAMs (2-5) for storing data output from the 11-bit shift register (1); A tri-state buffer 6-9 for controlling input and output of the plurality of 256-byte RAMs 2-5; An address generation ROM (10) for generating an address for storing data in divided portions for each channel of said plurality of 256-byte RAMs (2-5); A clock generator (11) for generating a clock for controlling the flow of all the data; A counter (12) for counting the clock of the clock generator (11) and outputting a predetermined signal to the address generation ROM (10); A 1x4 demultiplexer (13) for separating and outputting data deinterleaved from the plurality of 256-byte RAMs (2-5) for each channel; Word deinterleave circuit, characterized in that a plurality of inverters (14-16) are interconnected. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR89018650A 1989-12-15 1989-12-15 Word deinterleave circuit KR970006015B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR89018650A KR970006015B1 (en) 1989-12-15 1989-12-15 Word deinterleave circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR89018650A KR970006015B1 (en) 1989-12-15 1989-12-15 Word deinterleave circuit

Publications (2)

Publication Number Publication Date
KR910012917A true KR910012917A (en) 1991-08-08
KR970006015B1 KR970006015B1 (en) 1997-04-23

Family

ID=19292961

Family Applications (1)

Application Number Title Priority Date Filing Date
KR89018650A KR970006015B1 (en) 1989-12-15 1989-12-15 Word deinterleave circuit

Country Status (1)

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KR (1) KR970006015B1 (en)

Also Published As

Publication number Publication date
KR970006015B1 (en) 1997-04-23

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