KR910010635A - Lithography Process for Improved Overlay Accuracy - Google Patents

Lithography Process for Improved Overlay Accuracy Download PDF

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Publication number
KR910010635A
KR910010635A KR1019890017295A KR890017295A KR910010635A KR 910010635 A KR910010635 A KR 910010635A KR 1019890017295 A KR1019890017295 A KR 1019890017295A KR 890017295 A KR890017295 A KR 890017295A KR 910010635 A KR910010635 A KR 910010635A
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KR
South Korea
Prior art keywords
pattern
photoresist
alignment mark
chip
forming
Prior art date
Application number
KR1019890017295A
Other languages
Korean (ko)
Other versions
KR920006747B1 (en
Inventor
문승찬
Original Assignee
정몽헌
현대전자산업 주식회사
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Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890017295A priority Critical patent/KR920006747B1/en
Publication of KR910010635A publication Critical patent/KR910010635A/en
Application granted granted Critical
Publication of KR920006747B1 publication Critical patent/KR920006747B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

내용 없음.No content.

Description

중첩 정확도 향상을 위한 리소그라피(lithography) 공정방법Lithography Process for Improved Overlay Accuracy

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 실리콘 웨이퍼 상에 칩 절단영역 및 얼라인 마크가 형성된 상태를 나타낸 도면.1 is a view showing a state where a chip cutting region and an alignment mark are formed on a silicon wafer.

Claims (2)

실리콘 기판상에 1차 패턴용 물질을 형성하여 패턴 공정으로 칩에는 1차 패턴을 그리고, 칩과 칩사이의 절단영역 상에는 얼라인 마크를 형성하고 칩의 1차 패턴상부에 2차 패턴을 중첩시키는 공정방법이 있어서, 1차 패턴 및 얼라인 마크 상부에 2차 패턴용 물질을 형성하고 2차 패턴용 물질 상부에 포토레지스트를 도포한 다음, 절단영역의 얼라인 마크 상부의 포토레지스트를 선택적으로 노광시켜 노광된 영역의 포토레지스트를 제거하고 빛을 조사시켜 얼라인 마크의 좌표를 검출하여, 그로 이하려 포토레지스터의 도포상태 및 공기와 굴절율 차이로 발생하는 오차를 제거하는 것을 특징으로 하는 중첩 정확도 향상을 위한 리소그라피 공정방법.Forming the material for the primary pattern on the silicon substrate to form a primary pattern on the chip, and forming an alignment mark on the cutting region between the chip and the second pattern on the primary pattern of the chip by a pattern process In the process method, a second pattern material is formed on the first pattern and the alignment mark, a photoresist is applied on the second pattern material, and then the photoresist on the alignment mark of the cut region is selectively exposed. Improve the overlapping accuracy by removing the photoresist in the exposed area and irradiating light to detect the coordinates of the alignment marks, thereby eliminating errors caused by the application state of the photoresist and the difference between the refractive index and air. Lithography processing method for. 제1항에 있어서, 절단영역 상부의 얼라인 마크를 선택적으로 노광시키는 것은, 스태퍼(Stepper)에 장착된 마스크 블라인드(XL, XR, YB, YF)시스템을 사용하여 선택적으로 노공시키는 것을 특징으로 하는 중첩 정확도 향상을 위한 리소그라피 형성방법.The method of claim 1, wherein the exposure of the alignment mark on the upper part of the cutting area is selectively exposed by using a mask blind (XL, XR, YB, YF) system mounted on a stepper. Lithography forming method for improving the accuracy of nesting. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890017295A 1989-11-28 1989-11-28 Lithography process KR920006747B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890017295A KR920006747B1 (en) 1989-11-28 1989-11-28 Lithography process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890017295A KR920006747B1 (en) 1989-11-28 1989-11-28 Lithography process

Publications (2)

Publication Number Publication Date
KR910010635A true KR910010635A (en) 1991-06-29
KR920006747B1 KR920006747B1 (en) 1992-08-17

Family

ID=19292140

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890017295A KR920006747B1 (en) 1989-11-28 1989-11-28 Lithography process

Country Status (1)

Country Link
KR (1) KR920006747B1 (en)

Also Published As

Publication number Publication date
KR920006747B1 (en) 1992-08-17

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