KR910009313Y1 - Strobo circuit - Google Patents

Abstract

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Description

Strobe Function Execution Circuit

1 is a strobe function performing circuit of the present invention.

2a to 2b are strobe time interval conversion timing diagrams.

3a to 3e are timing charts when the strobe function is selected.

The present invention relates to a circuit for performing a strobo function in a digital VTR or a digital television that converts an analog video signal into a digital signal, stores it in a memory, and then converts the analog video signal into an analog video signal to display on a television screen.

Some conventional digital VTRs have a main screen strobe function. However, in the related art, in order to perform the main screen strobe function, a signal is required to perform a write operation in the memory for one vertical synchronization period during a predetermined period, and in order to change the execution cycle of the strobe function, the signal is used to perform the write operation. There are problems in that many logic gates are required as different cycles are used.

Accordingly, an object of the present invention is to provide a stroboscopic function performing circuit for generating a write signal having various types of stroboscopic function periods.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a detailed circuit diagram of a strobe function performing circuit of an embodiment according to the present invention.

Reference numeral 10 is a count unit for inputting the vertical synchronizing signal VS as a clock and connecting the strobe function selection signal STS for selecting whether to perform the strobe function to the reset terminal R to perform 8-bit counting. In the drawing, two 4-bit counters 11 and 12 are connected to each other and used instead of an 8-bit counter. Since the input data is grounded, the vertical synchronization signal VS is reset after being reset by the strobe function selection signal STS. Starts counting from 0.

Reference numeral 20 is an 8: 1 multiplexer which selects one of the signals output from the counting section 10. The reference numeral 20 receives a signal input from the line 1-line 5 and the line 6-line 8. One is selected and output to the line 9 by the control of the selection signal coming in.

Reference numeral 30 denotes a vertical write enable signal for allowing a memory to perform a write operation according to the signal output through the line 9 and the strobe function selection signal STS. And a deflip flag 32 for delaying the signal output through the line 9 by one field using the vertical synchronizing signal VS as a clock, and the line 9 Signal output through the inverted output of the flip-flop (32) ) And a strobe function selection signal inverted from the output of the AND gate 34. ) Is formed by the OR gate 36 generating the VWE.

Reference numeral 40 is a selection control unit for supplying a selection signal to the multiplexer 20 via lines 6, 7 and 8, an up / down counter 41 and the counter 41. Two negative logic gates (42), (47) and the counter for counting up to a first predetermined number (Q0 = 0, Q1 = 1, Q2 = 1, Q3 = 0) and no longer counting up Two negative logic gates 42, 48 and two halves to ensure that 41) counts up to the second integer (Q0 = 0, Q1 = 1, Q2 = 0, Q3 = 0) and no longer counts down It consists of electricity 45, 46.

2 and 3 are timing diagrams according to the present invention, and the code assignment of each waveform coincides with the reference numbers assigned to the input / output signals of FIG. 1 only for the same signal.

2 is a timing diagram showing a change in the strobe time interval, where STS is a strobe function selection signal applied to the reset terminal of the count unit 10 and the deflip plane 32, and STP is an up / down counter 41. FIG. The pulse is applied to the load terminal LD for loading, and the MIC-STR is a micom strobe signal (MIC-STR) input to the negative logic gates 42 and 43, and the UP is A count up enable signal input to the negative logic gate 42, DOWN is a count down enable signal input to the negative logic gate 43, S0, S1, S2 is a line (6), (7) , Selection signals S0, S1 and S2 applied to (8).

The CPU is an up count clock input to the up / down counter 41, and the CPD is a down count clock input to the up / down counter 41.

3 is a timing diagram at the time of selecting the strobe function when the selection signals S0 = 0, S1 = 0, and S2 = 1, VS is a vertical synchronization signal VS, and (T1 section is a section in which 16 vertical synchronization signals are generated). Section T2 indicates a section in which 32 vertical synchronization signals are generated).

STS is strobe function selection signal and 3S is output signal of line 3, Is the output of the deflip-flop 32, and VWE is the vertical write permission signal VWE.

The operation of FIG. 1 will be described with reference to the waveform diagrams of FIGS. 2 and 3.

When the strobe function is selected and the counting unit 10 operates, signals having different periods are output through the lines 1 through 5.

The line 1 outputs a signal indicating the period in which eight VS are generated, from which one rising edge to the next rising edge can record an image signal of eight fields. Through lines 2)-(5), a signal is generated indicating the period of time between 16, 32, 64, and 128 VSs, respectively, between any one rising edge and the next rising edge (for convenience, the line (1)). The signal output via the line 5 is referred to as a first to fifth period signal). As shown in the STS of FIG. 2, when the strobe function selection signal STS becomes " on " or " high " state, the counting unit 10 operates, and the up / down counter 41 is connected to the lines 6, ( 7) and 8, the multiplexer 20 outputs the third period signal by being loaded to output the selection signal in the state of S0 = 0, S1 = 0, S2 = 1. The third period signal is input to the def flip-flop 32 to As shown in Fig. 1, after a delay of one vertical synchronizing signal is generated, the signal is multiplied with the original third period signal input to the AND gate 34 and then input to the OR gate 36 to select an inverted strobe function. signal( ), The VWE signal is generated once every 32 vertical sync signals VS as shown in VWE of FIG.

Here, the output of the AND gate 34 is the inverted strobe function selection signal ( If the half-width strobe function is not selected, the VWM signal is always outputted in a high state so that a write operation can always be performed in the memory. In this state, when the count-up enable signal UP is input as shown in FIG. 2, the count-up signal is counted up at the falling edge of the microcomputer strobe signal MIC-STR of the up / down counter 41. The state of the selection signal output to (7), (8) changes to S0 = 1, S1 = 0, S2 = 1. As a result, the multiplexer 20 outputs the fourth period signal to generate the VWE signal once every 64 vertical synchronization signals VS.

Similarly, when the countdown enable signal is input, as shown in DOWN of FIG. 2, the up / down counter 41 counts down at the falling edge of the microcomputer strobe signal MIC-STR, and the multiplexer 20 generates a countdown signal. Two cycle signals are output to generate the VWE signal once for every 16 vertical sync signals (VS).

Meanwhile, each case in which the multiplexer 20 selects one of a plurality of input signals according to the states of the selection signals S0, S1, and S2 is as follows.

[table]

However, as shown in FIG. 1, since the three input terminals I0, I1, and I2 are grounded, the up / down count 41 is formed by four negative logic gates 42, 43, 44, and 48. In the state where the selection signals S0 = 1, S1 = 0, and S2 = 0, as shown in the CPD of FIG. 2, the down count clock is not generated and no further counts down, and the selection signals S0 = 0, S1 = 1, S2 In the state of = 1, the up count clock is not generated as shown in the CPU of FIG. 2 so that it no longer counts up. However, it is well known that when the input of the multiplexer 20 is eight, this counting limit is not required.

As described above, if the continuous input video signal is recorded in the memory once in a certain period and the data recorded in the memory is continuously displayed on the screen until the next recording operation is performed, the screen stops temporarily. After moving for a certain period of time, the user can see a screen in which the operation is broken for a certain period of time.

Although one embodiment has been described above, it can be easily configured within the scope without departing from the spirit of the present invention will be readily understood by those of ordinary skill in the art.

As described above, the present invention sets a reference for generating a signal having a different period by using a counter to make a plurality of memory write operation permission signals having different periods, and then controls the multiplexer with an up / down counter. By selecting only one of the outputs and using it to generate the write operation permission signal, not only a large number of logic gates can be generated, but also a write operation permission signal having various types of strobe periods can be easily generated. There is an advantage that can be easily adjusted.

Claims (1)

In digital VTD and digital television having a memory for recording and reading video signals, a counting unit counts signals having a plurality of periods in synchronization with the vertical synchronization signal VS according to the state of the strobe function selection signal STS. 10, a multiplexer 20 for selectively outputting one of the outputs of the counting unit 10 according to a predetermined selection signal input, a microcomputer strobe signal MIC-STR and an up count enable signal UP ) And a down count enable signal DOWN to input or down count the selection control unit 40 to control the output selection of the multiplexer 20 and a predetermined period output from the multiplexer 20. Delay the signal having one vertical synchronization signal generation period, and then logically multiply with the signal output from the multiplexer 20 and then logically sum the inverted signal (STS) of the strobe function selection signal. W strobe function performing circuitry, characterized in that a control signal generating section 30 for generating a normal write enable signal (VWE) to the memory.