JPH0970019A - Scanning converter and scanning conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of over-run scanning in advance by monitoring a time difference of write to an image memory and an end of read at all times from an image memory and conducting frame jump immediately when the time difference is smaller than a difference between input output frame periods. SOLUTION: In the case of sequentially writing an input image signal to four field memories 1-4 and reading the signal sequentially in different timings, a discrimination circuit 19 discriminates it that write addresses and read addresses are intricated when the difference from the frame period is larger than the time difference between the write and read end pulses. Then depending on the comparison result of a frame period of input output image signals outputted from a period comparison circuit 18, read/write memory control circuits 17, 16 are operated so as to make read/write while skipping two field memories to conduct frame jump.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention When the input image signal is converted into a different frame period and is output, when the writing and reading addresses are crossed on the image memory and so-called overtaking scanning occurs, this overtaking scanning is performed. The present invention relates to a scan conversion apparatus and a scan conversion method which are effective when an attempt is made to prevent an overtaking scan by jumping a read or write address before the occurrence.

[0002]

2. Description of the Related Art Japanese Patent Laid-Open Publication No. 64-46375 discloses a method for preventing the occurrence of an overtaking scan due to a difference in frame period. The prevention of occurrence of this overtaking scan will be described with reference to FIG. FIG. 9 is a block diagram of a conventional scan conversion device.

In FIG. 9, reference numeral 91 is an image memory composed of four field memories, 92 and 93 are write memory control circuits and read memory control circuits for controlling writing and reading of the image memory 91, and 94 is an outpacing detection circuit. is there.

In the scan conversion device configured as described above, when writing and reading are simultaneously started in the adjacent field memories, the detection circuit 94 soon detects that an overtaking scan will occur and detects the write memory control circuit 92 or the read memory control. A detection signal is sent to the circuit 93 to cause a frame jump at a write address or a read address to prevent overtaking scanning.

[0005]

However, in the above-mentioned conventional methods, there is no mention of the detailed overtaking detection method, and in order to surely prevent the overtaking scanning, the overtaking is actually performed. There is a problem that a frame jump for overtaking scanning is performed at a stage considerably earlier than the scanning interval, resulting in a high discontinuity occurrence rate and a deterioration in image quality.

The present invention solves the above problems and proposes a circuit for overtaking scanning detection, which reduces the frequency of discontinuity of output video signals, that is, less frame jumps for overtaking scanning prevention. An object of the present invention is to provide a scan conversion device and a scan conversion method that can realize excellent image quality.

[0007]

In order to achieve this object, the scan conversion apparatus of the present invention stores an input image signal.
An image memory consisting of a single field memory, a first field discriminating circuit for generating a field discriminating signal for discriminating whether the input image signal is an odd field or an even field, and at the beginning of the odd field of the input image signal. A first frame discrimination circuit that generates a frame discrimination signal that is synchronized and repeats inversion every two fields, a second field discrimination circuit that generates a field discrimination signal of an output image signal, and a frame discrimination signal of an output image signal A second frame discriminating circuit for controlling the writing, a writing memory control circuit for controlling writing to the field memory and generating a writing end pulse every two fields, and a reading end pulse for controlling reading from the field memory every two fields. And a read memory control circuit that generates A cycle comparison circuit that outputs the result of comparing the size of the frame cycles to the write and read memory control circuits and the determination circuit, a difference between the frame cycles of the input image signal and the output image signal, a write end pulse, and a read end pulse. The scan conversion method of the present invention has a structure in which a judgment circuit for comparing the time difference and judging execution of a frame jump is provided, and an input image signal is sequentially field data stored in an image memory composed of four field memories. When the data is stored as, and output after being converted into a different frame cycle, the input frame cycle is compared with the output frame cycle, and if the input frame cycle is larger than the output frame cycle, the writing is completed when the writing of the even field is completed. Pulse is generated and a read end pulse is issued when the odd field read is completed. Time difference from the write end pulse to the read end pulse is measured and compared with the difference between the input and output frame periods. If the difference between the frame periods is greater, two are returned from the field memory to be read and read. Continuing, if the input frame period is smaller than the output frame period, a write end pulse is generated when the odd field write is completed, and a read end pulse is generated when the even field read is completed. It is configured to measure the time difference until the writing end pulse and compare it with the difference between the input and output frame periods. If the difference between the frame periods is larger, two are skipped from the field memory to be written and writing is continued. Is.

[0008]

With this configuration, in the scan conversion apparatus and the scan conversion method of the present invention, when the input image signal is converted into a different frame period and then output, the write and read addresses are crossed on the image memory to cause overtaking scanning. In addition, it is possible to suppress the occurrence frequency of frame jumps to prevent this overtaking scanning, and by performing jumps on a frame-by-frame basis, fields such as even fields are written with odd field data. Inversion does not occur.

[0009]

【Example】

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a scan conversion device according to a first embodiment, FIG. 2 is a timing chart showing an example of how a field memory is selected during writing, and FIG.
FIG. 4 is a block diagram showing a first configuration example of the determination circuit in the first embodiment, and FIG. 4 is a timing chart showing the operation in the first configuration example of the determination circuit in the first embodiment.

In FIG. 1, 11 is an image memory composed of 4 field memories, and 12 and 13 generate field discrimination signals for discriminating whether the field is an odd field or an even field from the input synchronization signal and the output synchronization signal. Write and read field discrimination circuit, 1
4 and 15 are write and read frame discrimination circuits for discriminating frames by repeating inversion every two fields in synchronization with the start of an odd field, and 16 and 17
Is a write memory control circuit and a read memory control circuit for controlling writing and reading to and from the image memory 11 and generating a writing and reading end pulse for every two fields, and 18 is for controlling the frame period of the input and output image signals. A period comparison circuit for comparing and outputting the result, 19 is a determination for determining execution of a frame jump by comparing the difference between the frame periods of input and output image signals with the time difference between the end of writing and reading in the image memory 11. It represents a circuit.

In FIG. 3, reference numeral 31 is a count control circuit for controlling the counting operation, 32 is a cycle difference counting circuit for converting the difference between the input and output cycles into the number of clocks, and 33 is the time difference between the write and read end pulses. The time difference counting circuit 34 converts the clock into a period, and the reference numeral 34 represents a subtraction circuit that takes the difference between the clock numbers output from the period difference counting circuit 32 and the time difference counting circuit 33.

The operation of the scan conversion device configured as described above will be described below. The field discriminating circuit 12 and the frame discriminating circuit 14 on the writing side generate a field discriminating signal and a frame discriminating signal, respectively, from the horizontal and vertical synchronizing signals input together with the input image signal. These signals are input to the writing memory control circuit 16, and the field memories 1 to 4 in the image memory 11 are inputted.
Used for selection when storing the input image signal in. FIG. 2 shows an example of this state.

As shown in FIG. 2, write enable signals (low enable) to the field memories 1 to 4 are sequentially asserted according to the states of the field discrimination signal (O / E) and the frame discrimination signal (F1 / F2). To do. On the other hand, the field discriminating circuit 13 and the frame discriminating circuit 15 on the read side generate a field discriminating signal and a frame discriminating signal for reading from the output horizontal and vertical synchronizing signals. These signals are input to the read memory control circuit 17 and used to select the read of the field memories 1 to 4 in the image memory 11.

The write memory control circuit 16 and the read memory control circuit 17 control the writing and reading of the image memory 11, and determine the size of the frame period of the input / output image signal by comparing the respective vertical synchronizing signals. Based on the comparison result of the period comparison circuit 18, when the input frame period is larger than the output frame period, the write memory control circuit 16 outputs a write end pulse when writing to the even field and the read memory control circuit 17 outputs an odd number. When the reading of the data in the field is completed, a reading end pulse is generated. Conversely, when the input frame period is shorter, the write memory control circuit 16 outputs the write end pulse when the writing in the odd field is completed. Is the reading of even field data Teeth generates a read end pulse when finished, is input to the determination circuit 19.

The determination circuit 19 has, for example, the configuration shown in FIG. 3 and operates at the timing shown in FIG. 4 when the input frame period is longer than the output frame period. The count control circuit 31 synchronizes with the rising edge of the write end pulse, and the period difference count circuit 32 including a reversible counter and the time difference count circuit 3 including an up counter.
The count-up of 3 is started, and the count-up of both is stopped in synchronization with the rising edge of the read end pulse.

The time difference counting circuit 33 repeats the same operation in synchronization with the rising edges of the subsequent write end pulse and read end pulse, but the period difference count circuit 32.
Starts counting down in synchronization with the rising edge of the write end pulse from the previously counted number, and stops counting down in synchronization with the rising edge of the read end pulse. The subtraction circuit 34 subtracts the count number output from the period difference count circuit 32 from the count number output from the time difference count circuit 33, determines whether the count is positive or negative, and when negative, determines that overtaking scanning will occur soon. The frame jump permission signal is read out and output to the memory control means 17.

Referring to a timing chart in FIG. 4, both pulses are started by the time difference counting circuit 33 which starts the up-counting operation in synchronization with the write end pulse and ends the up-counting operation in synchronization with the read end pulse. Is represented by the clock numbers m, n, ... Further, as is apparent from FIG. 4, the write frame cycle is T1, and the read frame cycle is T2.
If the clock numbers are t1 clock and t2 clock, respectively, t1 + n = t2 + m is expressed. From this equation, the difference in frame period (T1-T
2) is the number of clocks, which can be expressed as t1-t2 = m-n. In other words, the consecutive 2 counted
The difference between the input and output frame periods can be obtained by taking the difference between the two time differences. As described above, the cycle difference counting circuit 32 includes one reversible counter, starts the up-count operation in synchronization with the write end pulse, and ends the up-count operation in synchronization with the read end pulse. The (m−n) clock is counted by starting the down-count operation from the previously counted number in synchronization with the next write end pulse and ending the down-count operation in synchronization with the next read end pulse. You can

By configuring the determination circuit 19 as described above, the difference between the frame periods can be obtained without measuring the size of the periods T1 and T2, and the circuit can be simplified. The count clock used is sufficiently faster than the frame frequency. Further, it is not necessary to count the difference between the frame periods many times, but it is also possible to hold the value counted once and store it in a register and load it each time it is necessary for subtraction. Further, the cycle difference counting circuit 32 may have a built-in subtractor and count the (mn) clocks by taking the difference between two consecutive count numbers output from the time difference counting circuit 33.

As described above, the scan conversion apparatus according to the first embodiment of the present invention constitutes an image memory from four field memories, and when the input image signal is converted into a different frame period and output, an overtaking scan occurs. To prevent this, control is performed so that writing and reading are not performed simultaneously on the same field memory. This is to constantly monitor the time difference between the end of writing to the memory and the end of reading from the memory, and when this time difference becomes smaller than the difference between the frame periods of input and output, the subsequent read or write end pulse is issued. This can be achieved by allowing a frame jump to occur before.

(Embodiment 2) Embodiment 2 of the present invention is Embodiment 1
The difference is that an integrating circuit is provided inside the determination circuit instead of using the counter.

FIG. 5 is a block diagram showing an example of the configuration of the determination circuit of the scanning conversion apparatus of the second embodiment. The overall configuration is the same as that of the first embodiment, that of FIG. 1, and FIG. 6 is the determination of the first embodiment. 6 is a timing chart showing the operation of the second configuration example of the circuit.

In FIG. 5, reference numeral 51 is a time difference measuring circuit for converting the rising time difference between the write end pulse and the read end pulse into a voltage value, and 52 is a cycle difference for converting the frame cycle difference between the input and output image signals into a voltage value. Measuring circuit,
Reference numeral 53 is a comparison circuit that compares the magnitudes of two voltage values output from the time difference measurement circuit 51 and the period difference measurement circuit 52.

The operation of the determination circuit of the scan conversion device configured as described above will be described below. The operations of the write and read field discrimination circuits 12 and 13, the frame discrimination circuits 14 and 15, the memory control circuits 16 and 17, and the period comparison circuit 18 are the same as those in the first embodiment. The determination circuit 19 has a configuration as shown in FIG. 5, for example,
When the input frame cycle is longer than the output frame cycle, the operation is performed at the timing shown in FIG.

The time difference measuring circuit 51 creates a positive pulse from the rising edge of the write end pulse to the rising edge of the read end pulse, and integrates this pulse to convert it into a voltage value. The cycle difference measuring circuit 52 takes the difference between two consecutive voltage values generated by the time difference measuring circuit 51. Comparison circuit 53
Compares the magnitudes of two voltage values emitted from the time difference measuring circuit 51 and the period difference measuring circuit 52, and when the voltage value emitted by the period difference measuring circuit 52 is larger, there is a possibility that overtaking scanning will occur soon. Judgment is made and a frame jump execution permission signal is read out to the memory control circuit 17.

This will be described with reference to FIG. 6. The time difference measuring circuit 51 generates a positive pulse which is a time difference pulse from the rising edge of the write end pulse to the rising edge of the read end pulse, and integrates this to generate voltage values V1 and V2. , ...
Then, the time difference between the write and read end pulses can be represented by the magnitude of the voltage value. When the writing and reading frame periods are T1 and T2, respectively, the frame period difference (T1-T2) is given by the difference between two consecutive voltage values generated by the time difference measuring circuit 51, for example (V1-V2). . The voltage values V1, V2, ... Generated by the time difference measurement circuit 51 and the voltage value (V1-V2) generated by the period difference measurement circuit 52 are input to the comparison circuit 53. When the generated voltage value (V1-V2) is larger, a frame jump execution permission signal is generated for the read memory control circuit.

By configuring the determination circuit 19 as described above, the integrator only needs to be built in the time difference measuring circuit 51, and accurate comparison can be performed without being affected by the variation due to the elements configuring the integrator. Become. The difference in frame period does not have to be measured many times, but may be measured once and then held and loaded each time a determination is made.

As described above, the scan conversion apparatus according to the second embodiment of the present invention constitutes the image memory from the four field memories, and when the input image signal is converted into different frame periods and output, an overscan is generated. To prevent this, control is performed so that writing and reading are not performed simultaneously on the same field memory. This is to constantly monitor the time difference between the end of writing to the memory and the end of reading from the memory, and when this time difference becomes smaller than the difference between the frame periods of input and output, the subsequent read or write end pulse is issued. This can be achieved by allowing a frame jump to occur before.

(Embodiment 3) Embodiment 3 of the present invention is Embodiment 1
Or, it is almost the same as 2 except that the difference between the input and output frame periods is compared inside the determination circuit without the period comparison circuit. FIG. 7 shows a third embodiment of the present invention.
FIG. 8 is a block diagram showing the scan conversion apparatus of FIG. 8, and FIG. 8 is a block diagram showing an example of the configuration of a determination circuit in the scan conversion apparatus of the third embodiment of the present invention.

In FIG. 7, reference numeral 78 compares the sizes of the input and output frame periods and outputs the result, and the difference between the frame periods of the input and output image signals and the time difference between the end of writing and reading in the image memory 11. A determination circuit that determines the execution of the frame jump by comparing with each other, and other circuits represent the same circuits as the circuits denoted by the same numbers in FIG.

In FIG. 8, reference numeral 85 denotes a period comparison / determination circuit capable of comparing the size of the frame period of the input / output image signal by determining whether the number of clocks generated by the period difference counting circuit 32 is positive or negative. 3 shows the same circuits as the circuits with the same numbers.

The operation of the scan conversion device configured as described above will be described below. The operations of the write and read field discrimination circuits 12 and 13, the frame discrimination circuits 14 and 15, and the memory control circuits 16 and 17 are the same as those in the first embodiment. The determination circuit 78 has the configuration shown in FIG. 8, for example, and operates in the following manner if the input frame period is longer than the output frame period in the initial state setting.

The count control circuit 31 starts counting up the period difference counting circuit 32 having a reversible counter and the time difference counting circuit 33 having an up counter in synchronization with the rising edge of the write end pulse, and the rising edge of the read end pulse. Stop counting up both circuits in synchronization with. The time difference counting circuit 33 repeats the same operation in synchronization with the rising edges of the subsequent writing end pulse and reading end pulse, but the period difference counting circuit 32 starts counting down in synchronization with the rising edge of the writing end pulse from the previously counted number. Then, the countdown is stopped in synchronization with the rising edge of the read end pulse.

The period comparison / judgment circuit 85 monitors whether the number of clocks output from the period difference counting circuit 32 is positive or negative. When the number is positive, the size of the frame period is the same as the initial state setting, and when it is negative, the initial state is set. A signal that is the opposite of the setting (in this case, the output frame period is larger than the input) is output to the write memory control circuit 16, the read memory control circuit 17, and the count control circuit 31 for writing and reading. Change the end pulse generation timing and the counter trigger signal.

In the case of this example, the write memory control circuit 16 and the read memory control circuit 17 are operated so that a write end pulse is generated at the end of writing in the odd field and a read end pulse is generated at the end of reading in the even field. The change is changed so that the start trigger signal of the counting operation of the time difference counting circuit 33 and the period difference counting circuit 32 becomes the read end pulse and the stop trigger signal becomes the write end pulse. The subtraction circuit 34 subtracts the count number output from the period difference count circuit 32 from the count number output from the time difference count circuit 33, and passes the result to the read control circuit 17.

In the scanning conversion apparatus according to the third embodiment, the comparison of the frame periods of the input and output image signals can be processed inside the determination circuit, and the circuit can be simplified.

Even when the determination circuit has the configuration of FIG. 5 in the second embodiment, it is possible to compare the sizes of the frame periods of the input and output image signals in the determination circuit by the same processing method.

[0037]

As described above, according to the present invention, when the image memory is composed of four field memories and the input image signal is converted into different frame periods and outputted, the writing to the image memory and the image memory are performed. Always monitor the time difference of the end of the read from, and when this time difference becomes smaller than the difference of the frame cycle of input and output, make the frame jump before the end pulse of the subsequent read. The occurrence of overtaking scanning can be prevented in advance, and the occurrence of discontinuity due to the overtaking scanning preventing operation can be suppressed to a low level.

Further, by making the jump in frame units, field inversion such as writing data of odd field into even field does not occur.

[Brief description of drawings]

FIG. 1 is a block diagram of a scan conversion device according to a first embodiment.

FIG. 2 is a timing chart of a field memory selection operation during writing in the first embodiment.

FIG. 3 is a block diagram of a configuration example of a determination circuit in the first embodiment.

FIG. 4 is a timing chart of the operation of the determination circuit according to the first embodiment.

FIG. 5 is a block diagram of a configuration example of a determination circuit according to the second embodiment.

FIG. 6 is a timing chart of the operation of the determination circuit according to the second embodiment.

FIG. 7 is a block diagram of a scan conversion device according to a third embodiment.

FIG. 8 is a block diagram of a determination circuit according to a third embodiment.

FIG. 9 is a block diagram of a conventional scan conversion device.

[Explanation of symbols]

 Reference Signs List 11 image memory 12 write field determination circuit 13 read field determination circuit 14 write frame determination circuit 15 read frame determination circuit 16 write memory control circuit 17 read memory control circuit 18 period comparison circuit 19 determination circuit 31 count control circuit 32 period difference count circuit 33 Time difference counting circuit 34 Subtraction circuit 51 Time difference measurement circuit 52 Period difference measurement circuit 53 Comparison circuit 78 Judgment circuit 85 Period comparison judgment circuit 91 Image memory 92 Write memory control circuit 93 Read memory control circuit 94 Detection circuit

Claims (8)

[Claims] 1. A four field memory for storing an input image signal, and a first field discriminating circuit for generating a field discriminating signal for discriminating whether the input image signal is an odd field or an even field. , 2 in synchronization with the start of the odd field of the input image signal
A first frame discriminating circuit that generates a frame discriminating signal that repeats inversion for each field; a second field discriminating circuit that generates a field discriminating signal of an output image signal;
A second frame discriminating circuit that generates a frame discriminating signal of the output image signal, a write memory control circuit that controls writing to the field memory and generates a write end pulse every two fields, and reading to the field memory And a read memory control circuit for generating a read end pulse for every two fields, a period comparison circuit for outputting the result of comparing the frame periods of the input image signal and the output image signal, and the input image signal. A determination circuit that determines the execution of a frame jump by comparing the difference between the frame periods of the output image signals and the time difference between the write end pulse and the read end pulse. When writing sequentially to the field memory and reading sequentially at a different timing than writing, In the determination circuit, when the difference between the frame periods is larger than the time difference between the write and read end pulses, it is determined that the write and read addresses intersect, and the next frame is read or read according to the output of the period comparison circuit. A frame jump is performed when writing is started, and the read memory control circuit or the write memory control circuit is operated so as to skip or read or write the two field memories from the reading or writing order to perform the frame jump. Characteristic scan conversion device. 2. The determination circuit includes a count control circuit, a time difference counting circuit, a period difference counting circuit, and a subtraction circuit, and the count control circuit controls the operations of the time difference counting circuit and the period difference counting circuit. The time difference counting circuit starts counting up of the counter in synchronization with one pulse of the first signal, and stops counting up in synchronization with one pulse of the second signal, so that the time difference between the two pulses becomes the number of clocks. The period difference counting circuit starts counting up of the reversible counter in synchronization with one pulse of the first signal, and stops counting up in synchronization with one pulse of the second signal. The time difference is measured by the number of clock pulses, the countdown is started in synchronization with the subsequent one pulse of the first signal, and the subsequent count of the second signal is started. The difference between the periods of the two signals is converted into the number of clocks by stopping the countdown in synchronization with one pulse, and the subtractor circuit outputs the number of clocks sequentially output by the time difference count circuit and the clock output by the period difference count circuit. 2. The scan conversion apparatus according to claim 1, wherein a frame jump is determined when a difference from the number is taken and the output of the subtraction circuit is negative. 3. The determination circuit includes a time difference measuring circuit, a period difference measuring circuit, and a comparing circuit, and the time difference measuring circuit is a first circuit.
Output a voltage value proportional to the time from the rise of one pulse of the signal of to the rise of the one pulse of the second signal,
The cycle difference measuring circuit outputs a difference between two consecutive voltage values output by the time difference measuring circuit, and the comparison circuit outputs a voltage value sequentially output by the time difference measuring circuit and a voltage value output by the cycle difference measuring circuit. 3. The scan conversion device according to claim 1, wherein the frame jump is determined to be necessary when the voltage value output from the period difference measuring circuit is larger than the above. 4. A determination circuit includes a count control circuit, a time difference counting circuit, a period difference counting circuit, a subtraction circuit, and a period comparison determination circuit, and the count control circuit operates the time difference counting circuit and the period difference counting circuit. The time difference counting circuit starts counting up of the counter in synchronization with one pulse of the first signal, and stops counting up in synchronization with one pulse of the second signal. The time difference is converted into the number of clocks, and the cycle difference counting circuit starts the count-up of the reversible counter in synchronization with one pulse of the first signal and stops the count-up in synchronization with one pulse of the second signal. , The time difference between pulse inputs is measured by the number of clock pulses, the countdown is started in synchronization with the subsequent one pulse of the first signal, and the second signal is output. By stopping the countdown in synchronism with the subsequent 1 pulse of, the period difference between the two signals is converted into the number of clocks, and the period comparison / determination circuit inputs the positive / negative of the number of clocks generated by the period difference determination circuit. The subtraction circuit determines the magnitude relationship between the frame periods of the image signal and the output image signal, the subtraction circuit takes the difference between the number of clocks sequentially output by the time difference counting circuit and the number of clocks output by the period difference comparison circuit, and the subtraction circuit 2. The scan conversion apparatus according to claim 1, wherein the cycle comparison circuit is deleted by determining that the frame jump is necessary when the output of the above is negative. 5. The write memory control circuit generates a write end pulse when the writing of the even field is completed when the frame period of the input image signal is larger than the frame period of the output image signal, and writes the odd field when it is smaller. When the frame period of the input image signal is larger than the frame period of the output image signal, the read memory control circuit generates a read end pulse when the reading of the odd field is finished. The scan conversion device according to claim 1 or 4, wherein, when smaller, a read end pulse is generated when the reading of the even field is completed. 6. When the input image signal is sequentially stored as field data in an image memory composed of four field memories, converted into different frame periods and sequentially output, the input frame period is compared with the output frame period. If it is larger, a write end pulse is generated when the writing of the even field is completed, a read end pulse is generated when the reading of the odd field is completed, and the time difference from the write end pulse to the read end pulse is measured and input. And a difference between the frame periods of the output image signals, and when the difference between the frame periods of the input and output image signals is larger, a frame jump is performed, and two readings are returned from the field memory to be read and the reading is continued. , If the input frame period is smaller than the output frame period, odd A write end pulse is generated when the field write is completed, a read end pulse is generated when the even field read is completed, the time difference from the read end pulse to the write end pulse is measured, and the input and output images are displayed. Compared with the difference in signal frame period, when the difference in frame period between the input and output image signals is larger, a frame jump is performed, and two are skipped from the field memory to be written, and writing is continued. Scan conversion method. 7. When the input image signal is sequentially stored as field data in an image memory composed of four field memories, converted into different frame periods and sequentially output, the input frame period is compared with the output frame period. If it is larger, the counter starts counting up in synchronization with 1 pulse of the write end pulse and 1 pulse of the read end pulse.
Stop counting up in synchronization with the pulse, convert the time difference from the write end pulse to the read end pulse into the number of clocks, start counting up the reversible counter in synchronization with one pulse of the write end pulse, The count-up is stopped in synchronization with one pulse of the read end pulse, the countdown is started in synchronization with one pulse subsequent to the write end pulse, and the countdown is synchronized with one pulse subsequent to the read end pulse. Stop and convert the difference between the cycles of the write end pulse and the read end pulse into the number of clocks, and from the clock number of the time difference from the write end pulse to the read end pulse, the cycle of the write end pulse and the read end pulse If the number of clocks of the If the input frame cycle is shorter than the output frame cycle, the counter starts counting up in synchronization with one pulse of the read end pulse. Then, counting up is stopped in synchronization with one pulse of the write end pulse, the time difference from the read end pulse to the write end pulse is converted into the number of clocks, and reversible in synchronization with one pulse of the read end pulse. The counter starts counting up, stops counting up in synchronization with one pulse of the write end pulse, starts counting down in synchronization with one pulse subsequent to the read end pulse, and starts counting down in synchronization with one pulse of the write end pulse. The countdown is stopped in synchronization with one pulse, and the reading end And the number of clocks of the difference between the periods of the read end pulse and the write end pulse are converted from the number of clocks of the time difference from the read end pulse to the write end pulse to the number of clocks. A scan conversion method characterized by performing frame jump when subtraction is negative, skipping two from the field memory to be written, and continuing writing. 8. When the input image signal is sequentially stored as field data in an image memory composed of four field memories, converted into different frame periods and sequentially output, the input frame period is compared with the output frame period. If it is larger, a positive pulse is generated from the rising edge of one pulse of the write end pulse to the rising edge of one pulse of the read end pulse, integrated, converted into a first voltage value, and similarly the second voltage obtained subsequently. The value is compared with a value obtained by subtracting the second voltage value from the first voltage value, and when the second voltage value is smaller, a frame jump is performed, and two are returned from the field memory to be read. If reading is continued and the frame period of the input is smaller than the frame period of the output, write from the rising edge of one pulse of the read end pulse The positive pulse is generated until the rising of one pulse of the end pulse of integration, is integrated, is converted into the first voltage value, and similarly, the second voltage value and the first voltage value obtained subsequently are used to the second voltage value. The scan conversion method is characterized in that a frame jump is performed when the second voltage value is smaller, and two are skipped from the field memory to be written and writing is continued. .