KR910008957A - Voltage Switching Circuits for Logic Arrays - Google Patents

Abstract

No content

Description

Voltage Switching Circuits for Logic Arrays

As this is a public information case, the full text was not included.

2 is a block diagram of a fixed memory device using the acceleration circuit of the present invention;

3 is a flow chart showing the logic state of the present invention;

4 schematically illustrates a preferred embodiment of the present invention.

Claims (17)

A circuit for providing fast switching of a logic array comprising a plurality of generation lines, and an output capable of generating high and low logic states, the circuit being coupled to the generation line and capable of generating current through the generation line. And a control circuit capable of controlling the generated current in response to the output logic state. 2. The control circuit according to claim 1, wherein the control circuit is capable of increasing the current generated by the current generating circuit in response to the first logical state and reducing the current generated by the current source circuit in response to the second logical state. And a circuit coupled to the current generating circuit. 2. The circuit of claim 1, wherein the control circuit is coupled to the memory output and is coupled to the sensing circuit capable of detecting a state of the memory output, and is coupled to the sensing circuit and controls the current generated by the current generating circuit. A circuit comprising a switching control circuit capable of 2. The device of claim 1, wherein the current generating circuit has an anode coupled to the switching circuit and a cathode coupled to ground, the diode capable of setting a voltage level, and capable of generating a current in response to the voltage level. A circuit comprising a plurality of transistors, 4. The circuit of claim 3, wherein the sense circuit comprises a differential transistor pair coupled between the memory output and the switching circuit. 6. The transistor of claim 5, wherein the differential transistor pair comprises: a first NPN sensing transistor having an emitter coupled to a current source, a base coupled to the memory output and a collector coupled to the switching circuit, and an emitter coupled to the current source, And a second sensing NPN transistor having a base coupled to a reference voltage and a collector coupled to the switching circuit. The between 8. The method of claim 6, wherein the detection circuit is a first coupled between the first sense transistor and the collector and the voltage supply (V _S) resistor and the collector and the voltage supply (V _S) of said second sense transistors 2 A circuit comprising a resistor. 4. The switching circuit of claim 3, wherein the switching circuit comprises: an emitter coupled to the current generating circuit, a base coupled to the second sense transistor, a first NPN sense transistor having a collector coupled to V _CC , and the memory output; And a second NPN sensing transistor having a coupled emitter, a base coupled to the collector of the first sensing transistor, and a collector coupled to V _CC . The switching circuit of claim 8, wherein the switching circuit comprises: a first resistor coupled between the emitter of the first switching transistor and the anode of the diode of the current generating circuit; and the emitter of the second switching transistor; And a second resistor coupled between the memory outputs. A method for providing fast switching of a logic array comprising a plurality of generation lines and an output capable of generating high and low logic states, the method comprising: sensing a logic state of an output, and in response to the sensed state Controlling the current through the production line. 12. The method of claim 10, wherein the controlling step includes increasing the current through the production line when the output is in the first logical state, and decreasing the current through the production line when the output is in the second logical state. How to feature. 11. The method of claim 10, wherein said sensing step includes comparing said memory output state with a fixed reference voltage. 13. The method of claim 12, wherein the comparing step comprises driving a first sense transistor of a differential transistor pair to the output, and when the memory output is in a high logic state, the first sense transistor is turned off and the second The sense transistor is turned on; Driving the second sense transistor of the differential transistor pair to a reference voltage such that the first sense transistor is turned on when the memory output is in a low logic state and the second sense transistor is turned off. Way. 11. The method of claim 10, wherein said first logical state is a high logic state and said second logical state is a low logic state. 11. The method of claim 10, wherein said controlling step comprises controlling a current source with a switching transistor. 11. The method of claim 10, further comprising pulling up the generation line in response to the second logical state. 17. The method of claim 16, wherein said pulling up further comprises switching a switching transistor coupled to said generation line and a voltage source to a high state. ※ Note: The disclosure is based on the initial application.