KR100216434B1 - Voltage switching circuit for logic arrays - Google Patents

Abstract

The memory device 10 anticipates the next state of the output of the memory device 12, and sense and control circuitry 24 for turning on and off the current source 20 in response to the memory output to provide a high speed output transistor. A switching circuit 22 composed of 26.

Description

Voltage switching circuit for logic array

1 is a schematic illustration of a fixed memory element of the prior art;

2 is a block diagram of a fixed memory device using the acceleration circuit of the present invention.

3 is a flow chart showing the logical state of the present invention.

4 schematically illustrates a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: PAL memory device 15: logic matrix

18: differential pair circuit 22: switching circuit

24: sensing circuit 26: current switching circuit

The present invention relates generally to integrated circuits, and more particularly to voltage switching circuits for logic arrays.

In the design of integrated circuits, a particular emphasis is placed on the operating speed of the circuits.

In fixed-memory devices such as programmable array logic (PAL), a current source is coupled to each generation line of the PAL primarily to reduce the product line high-to-low transition time.

In operation, the current source remains on continuously. When the inputs to all emitter follower transistors connected to the generation line are low, it is desirable that the logic level on the generation line is low. By pulling down the emitter follower associated with the production line, the current source turns off the emitter follower more quickly than when there is no current source. As a result, the production line is also quickly pulled down.

If one of the inputs is high, the logic level on the generation line is also preferably high. In order for the emitter follower connected to the high input to turn on, it must overcome the pull down from the current source. This requires more than is required without a current source.

Therefore, while such a circuit is faster than PAL without a current source, there is a disadvantage in that the power consumption by the device is greatly increased. Another disadvantage is that increasing the current to increase the high-to-low transition rate also reduces the low-to-high transition rate.

Accordingly, there is a need to provide a circuit for providing a high high-to-low generation line transition rate without increasing the low-to-high transition rate and further increasing the power consumption of the device.

According to the present invention, a switching circuit is provided which greatly increases the signal transition rate on the production line of a logic array.

A switching circuit for detecting the current state of the production line is provided. When the circuit detects that the current state of the memory output is at a high logic level, multiple current sources generate an increased current through the production line. When the sensing circuit detects that the current output state is low level, the current generated by the current source is reduced. At the same time, a voltage is supplied to the memory output to allow the output to transition to a higher state more quickly.

The circuit of the present invention can be used with any fixed memory element such as PAL or ROM. Thus, the circuit of the present invention has the technical advantage of providing a faster transition of the production line of the memory in both directions, eliminating unnecessary and wasted power consumption when no current source is needed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic illustration of a prior art programmable array logic (PAL) memory device, which is generally incorporated by reference numeral 10. Emitter follower 12 and diode 14 form a logical matrix 15 whose output at node 16 is a function of input signal S1-SM. The emitter of each transistor 12 in each column C1 to CN is coupled to the production lines PL1 to PLN. The anode of each diode 14 is coupled to node 16 and the cathode is coupled to generation lines PL1 to PLN. The matrix output at node 16 forms the input of differential pair circuit 18 having a complement output and a true output OUT1 and OUT2, respectively. The current source 20 is coupled between each generation line PL1 through PLN and ground.

In operation, when the inputs S1 to SM, ie each transistor 12 coupled to the production line, are low, the current source 20 will pull down the production line coupled to it. When one or more transistors 12 in a particular column are turned on, the associated generation line is in a high logic state. More current from current source 20 pulls down the production line faster than is possible with less current, increasing the high-to-low transition rate. However, this current, which is continuous in the prior art, makes it more difficult for the transistor 12 to pull up the production line to a high logic level.

2 shows a block diagram of the switching circuit 22 of the present invention coupled to a prior art logic array. Signals S1-SM form an input to logic matrix 15, including transistor 12, and node 16 forms an output. The current source 20 is coupled to the production lines PL1 to PLN and is brought high and low by the switching circuit 22 of the present invention. As described in detail with respect to FIG. 4, the switching circuit 22 has a sense input for detecting the logic state of the output 16, and a pull up operable to pull up the matrix output during a low-to-high transition. It is connected to an output node 16 using the output.

3 is a flow chart showing the logic sequence of the present invention shown in FIG. In block 23a, the current state of the matrix 15 output from the node 16 is investigated. If the current state is high, the circuit assumes that the next state will be low (block 23b) and increases the current through current source 20 at block 23c. The pull up output of the switching circuit 22 is reduced at block 23d. If the current state corresponds to a low logic level at block 23a, the circuit assumes that the next state will be a high logic level (block 23e) and reduces the current through current source 20 at block 23f. . At the same time, the pull up output of the switching circuit 22 is increased (block 23g), providing a faster pull up for the matrix output during the low-to-high transition.

4 schematically shows a preferred embodiment of the switching circuit 22 of the present invention. The input of the sense circuit 24 is coupled to the output of the memory matrix at node 16. The true and complement outputs of the sense circuit 24 are coupled to a current switching circuit 26 having an output 27a coupled to the current source 20 and an output 27b coupled to the node 16.

Sense circuit 24 includes a differential pair circuit formed of transistors 28 and 30, current source 32, and bias resistors 34 and 36. The base of the input transistor 28 is coupled to the node 16, the emitter of which is coupled to the current source 32 and the emitter of the input transistor 30, and the collector of which is coupled to one end of the resistor 34. The base of the input transistor 30 is coupled to the reference voltage V _REF , and the collector is coupled to one end of the resistor 36. The other ends of resistors 34 and 36 are coupled to voltage wins V _S , respectively. The collectors of the input transistors 28 and 30 each comprise a complementary output and a true output of the sense circuit 24.

Current switching circuit 26 includes transistors 38 and 40 coupled to sense circuit 24, resistor 42 coupled to current source 20, and resistor 44 coupled to node 16. The base of the switching transistor 38 is coupled to the collector (true output) of the input transistor 30, the collector is coupled to Vcc, and the emitter is coupled to one end of the resistor 42. The base of the switching transistor 40 is coupled to the collector (repair output) of the input transistor 28, coupled to the collector Vcc, and the emitter is coupled to one end of the resistor 44. The other end of the resistor 42 is coupled to the current source 20, and the other end of the resistor 44 is coupled to the node 16.

The current source transistors 20 include bases coupled to the output 27a of the switching circuit 26, emitters coupled to ground, and collectors coupled to the production lines PL1-PLN. The anode is coupled to the other end of the resistor 42 of the switching circuit 26 and its cathode is coupled to ground.

In operation, differential input pair transistors 28 and 30 sense the current state of the matrix output at node 16. If the state is high, the input transistor 28 is turned on and the input transistor 30 is switched to the low state. Next, the switching transistor 40 is turned off and the switching transistor 38 is switched to the high state. Thus, the switching transistor 38 allows a larger amount of current to flow through the resistor 42, increasing the current source 20. Diode 46 provides a reference voltage for current source 20. Since the current source 20 is high, when the signal at node 16 transitions to a low logic level, the circuit is ready to pull down the production lines PL1-PLN.

If the matrix output at node 16 is at a low logic level, input transistor 28 is turned off and input transistor 30 is turned on. The switching transistor 38 is switched to the low state, and the switching transistor 40 is switched to the high state. Since the switching transistor 38 is low, less current flows through the resistor 42 and the current source 20 goes low, thereby reducing unnecessary power consumption. Since current source 20 drives low current while output 16 is low, subsequent low-to-high transitions are not prevented by the current source. Moreover, because the switching transistor 40 is high, a larger amount of current flows through the resistor 44, so that the matrix output at the node 16 quickly pulls up to a high logic level at a suitable time.

As a result, the present invention provides a technical advantage that allows a faster transition in both the high-to-low direction and the low-to-high direction, while reducing unnecessary power consumption.

Although the present invention has been described with respect to bipolar technology, it should be noted that other techniques such as CMOS may also be used.

While the invention has been described in detail, it should be understood that various changes, applications, and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

A circuit for providing fast switching of a logic array having a plurality of product lines, and an output operable to generate high and low array output logic states, the circuit being coupled to the production lines, the production line: Through which the current generating circuit operable to generate first and second nonzero magnitudes of current and the first and second nonzero magnitudes of current according to the array output logic state. A control circuit, the current generating circuit having an anode coupled to the control circuit, and a cathode coupled to ground, the diode being operable to set a voltage level; And a plurality of transistors operable to generate. The second array output logic state of claim 1, wherein the control circuit is coupled to the current generation circuit to increase the current generated by the current generation circuit to the first magnitude in accordance with a first array output logic state. And circuitry operable to reduce the current generated by the current generating circuit to the second magnitude. 2. The control circuit of claim 1, wherein the control circuit is coupled to the array output and is coupled to the sensing circuit and operable to detect a state of the array output to operate to control the current generated by the current generating circuit. And a possible switching control circuit. 4. The circuit of claim 3, wherein the sense circuit comprises a differential transistor pair coupled between the array output and the switching control circuit. 5. The transistor of claim 4, wherein the differential transistor pair is coupled to the first NPN sense transistor and the current generating circuit having an emitter coupled to a current source, a base coupled to the array output, and a collector coupled to the switching control circuit. And a second NPN sense transistor having an emitter, a base coupled to a reference voltage, and a collector coupled to the switching control circuit. 6. The voltage sensing circuit of claim 5, wherein the sensing circuit comprises: a first resistor coupled between the collector of the first NPN sense transistor and a voltage source Vs and a second coupled between the collector and voltage source Vs of the second NPN sense transistor. The circuit further comprises a resistor. 4. The sensor of claim 3, wherein the sense circuit comprises: a first NPN sense transistor having an emitter coupled to the current generating circuit, a base coupled to the collector of the second NPN sense transistor, and a collector coupled to Vcc; And a second NPN sense transistor having an emitter coupled to the array output, a base coupled to the collector of the first NPN sense transistor, and a collector coupled to Vcc. 8. The apparatus of claim 7, wherein the switching control circuit comprises a first resistor coupled between the emitter of the first NPN sense transistor and the anode of the diode of the current generation circuit, and the emitter of the second NPN sense transistor. And a second resistor coupled between the array output. A method of providing fast switching of a logic array having a plurality of product lines and an output operable to generate first and second logic states, the method comprising: a terminal for sensing a logic state of the array output, and According to the sensing state, selecting one of the first and second nonzero magnitudes of current generated through the generation line to control the current through the generation lines, thereby providing the logic A plurality of transistors in which a state is sensed by a diode operatively coupled to the array output, wherein the one of the first and second non-zero magnitudes of the current is operable to generate a current in accordance with the sensed logic state. Selected by the method. 10. The method of claim 9, wherein the controlling step includes increasing the current through the generation lines to the first magnitude when the array output is in a first logic state, and when the array output is in a second logic state. Reducing the current through the production line to the second magnitude. 3. The method of claim 2, wherein said sensing step comprises comparing said array output state to a fixed reference voltage. 12. The method of claim 11, wherein the comparing step includes driving a first sense transistor in the differential pair to the array output, and driving a second sense transistor in the differential pair to a reference voltage. The first sense transistor is turned off and the second sense transistor is turned on when the array output is in a high logic state, and the first sense transistor is turned on and the second sense transistor is turned on when the array output is in a low logic state. And the sense transistor is turned off. 10. The method of claim 9, wherein the first logic state comprises a high logic state and the second logic state comprises a low logic state. 10. The method of claim 9, wherein said controlling step comprises controlling a current source with a switching transistor. 15. The method of claim 13, further comprising increasing the voltage of the generation lines in accordance with the first logic state. 16. The method of claim 15, wherein increasing the voltage comprises switching a switching transistor coupled to the generation lines and a voltage source high.