JPH03187520A - Circuit and method for performing rapid change-over of logic array - Google Patents

Abstract

PURPOSE: To increase the switching speed of a product line without increasing the power consumption of a device by sensing the logical state of an output and controlling a current passing the product line in response to the sensed state. CONSTITUTION: The current state of a matrix 15 outputted to a node 16 is inspected. When the current state is high, the succeeding state of the circuit is supposed to be low, a current passing a current source 20 is increased and the rise output of a switching circuit 22 is reduced. When the current state corresponds to a low logical level, the succeeding state of the circuit is supposed to be a high logical level, the current passing the current source 20 is reduced, the rise output of the circuit 22 is increased, and at the time of switching from low to high, the output of the matrix 15 is more quickly raised. Consequently the product line of a memory can be quickly switched in both directions from high to low and from low to high while reducing unnecessary power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to integrated Li circuits, and more specifically, to
Apply to the voltage switching circuit for the logic array.

In conventional technology and road design, great emphasis is placed on the operating speed of the circuit. programmable array theory
In a fixed memory device such as fi (PAL), a current source is often coupled to each WAIIa of the PAL to reduce the high-to-low transition time of the line product.

To explain the operation, i! The current source remains on continuously. Mill
It is a blessing that the logical level of is starvation. 1l on the stack line
The II3I source "pulls down" the emitter followers, turning them off more quickly than without the current source. As a result, the 11EA will also be lowered immediately.

When one of the inputs is high, it is desired that the logic level of the product line also be high. Emitter connected to high input
In order to turn on the follower, it is necessary to overcome the pull down from the current source.

This requires even more current than without the current source.

Therefore, this circuit is faster than PAL without current sources, but has the disadvantage that it significantly increases the power consumed by II. Another drawback is that increasing the current to increase the high to low switching speed reduces the low to high switching speed.

Therefore, it became necessary to create a circuit that would increase the switching speed of the high to low stack line without increasing the low to high switching Ttrx and without increasing the power consumption of the device. .

SUMMARY OF THE INVENTION The present invention provides a switching circuit that significantly increases the switching speed of the M line of a logic array.

A switching circuit detects the current state of the m line.

When the circuit detects that the current state of the memory output is at a high logic level, the plurality of current sources increases the current through the foil wire. When the sensing circuit detects that the current output state is a low level, the current generated in the current source is reduced. At time n, a voltage is applied to the output of the memory, allowing the output to more quickly switch to a high state.

The circuit of this invention can be used in any fixed memory device such as PAL or ROM. Therefore, the circuit of the present invention has the technical advantage of providing faster switching of memory #am in both directions while eliminating unnecessary wasted power consumption when the N current source is not needed. has.

In order that the invention and its advantages may be better understood, reference will now be made to the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiment of the invention is best understood with reference to FIGS. 1-4 of the drawings. The same reference numerals are used for like parts throughout the drawings.

Figure 1 shows conventional 10-gram multiple array logic (PAL)
1 is a circuit diagram of a memory device, which is generally designated by the reference numeral 1.
Indicated by 0. Emitter follower 12 and diode 14
forms a logic matrix 15, whose output on Wi16 is a function of the input signals S1-8M. Each column Cl
-The vines of each transistor 12 in CN are MI
iPLl-PLN. each diode 14
the anode of is coupled to node 16 and the cathode of the product mPL1-PLN
is combined with The output of the matrix of j116 becomes the input to a differential pair circuit 18 having complement and antilog outputs 0UTI and 0UT2, respectively. Current source 20//each +7)
MIIPL1-PLN is coupled between PLN and ground.

In operation, when each input S 1-8M coupled to the product line, and thus each l resistor 12, is low, current 120 pulls down the product line to which it is coupled. When one or more transistors 12 in a particular column turn on, f113! The product line is pulled to a high logic state. The significantly larger current from the salt 51 source 20 pulls the stack down faster than would be possible with a heavier Wl flow, increasing the high-to-low switching speed. However, this Wi current, which was conventionally continuous, makes it more difficult for transistor 12 to pull 5sst to a high logic level.

FIG. 2 is a block diagram of a switching circuit 22 of the present invention coupled to a conventional logic array. Signals S1-8M become the inputs of a logic matrix 15 made up of transistors 12, and 1i16 forms the output. tlklt20 is coupled to rfRJQPL1-pLN and is turned high and low by the switching circuit 22 of the present invention. A switching circuit 22 has a sensing input for detecting the logic state of the output 16 and a pull-up which can act to pull up the output of the matrix during low-to-high switching, as will be explained in more detail below with reference to FIG. The output is connected to the output 1116 using the output.

FIG. 3 is a flowchart showing the logical sequence of the circuit of the present invention shown in FIG. In block 23a, the current state of matrix 15 exiting node 16 is checked. If the current state is high, the circuit assumes that the next state is low (block 23b) and in block 23c, l! through the current source 20! Increase flow. In block 23d, the pull-up output of the vJ switching circuit 22 is lowered. In block 23a, if the current state corresponds to a low logic level, the circuit assumes that the next state is a high logic level (block 23e);
At block 23f, the vli flow through M flow 120 is reduced. Face to face, Switch II! Pulling I fl 22 increases the E output (block 23g), causing a -II fast pull of the matrix output when switching from low to high.

FIG. 4 is a circuit diagram of a preferred embodiment of switching circuit vR22 of the present invention. The input to the sensing circuit 24 is coupled to the output of the memory matrix at v16. Sensing circuit 24
The true and complement outputs of output 2 are coupled to current source 20.
1 with output 27b coupled to 7a and 116! It is coupled to the flow switching circuit m26.

The sensing circuit 24 consists of a differential pair formed by transistors 28.30, a current source 32, and a bias resistor 34.36. The base of input transistor 28 is coupled to node 16, its emitter is coupled to current source 32 and the emitter of input transistor 30, and its collector is coupled to resistor 3.
It is connected to one end of 4. The base of input transistor 3o is coupled to the ls quasi-voltage (V RE F ), and the collector is coupled to one end of resistor 36 . The other ends of resistors 34 and 36 are both coupled to voltage wAvs. The collectors of human power transistors 28, 30 provide the complement and antilog outputs of sensing circuit 28, respectively.

The switching circuit 26 is comprised of a transistor 38 , 40 coupled to the sensing circuit 24 , a resistor 42 coupled to the current [ 20 , and a resistor 44 coupled to the node 16 . The base of switching transistor 38 is coupled to the collector (antilog output) of input transistor 30, the collector is coupled to vcc, and the emitter is coupled to one end of resistor 42. The base of switching transistor 40 is coupled to the collector (complement output) of input transistor 28, the collector is coupled to vcc, and the emitter is coupled to one end of resistor 44. The other end of resistor 42 is coupled to power supply 81 source 2o, and the other end of resistor 44 is coupled to node 16.

Current source transistor 20 has a base coupled to output 27a of switching circuit 26, an emitter coupled to ground, and
A collector is coupled to live wire 1'L 1-PLN.

The anode of diode 46 is coupled to the other end of resistor 42 of switching circuit 26, and the cathode of diode 46 is coupled to ground.

In operation, differential input pair 28.30 senses the current state of the matrix outputs at node 16. When this condition is high, input transistor 28 turns on and input transistor 30 switches low. This turns off switching transistor 40 and switches switching transistor 38 high. Therefore, switching transistor 38 allows more current to flow through resistor 42, increasing N current 1120. Diode 46 provides a voltage reference for current source 20. When current source 20 is high, the circuit is ready to pull down live lines PL1-PLN when the signal at jl16 switches to a low logic level.

[When the matrix output of 16 is at a low logic level, input transistor 28 is turned off and human power transistor 30 is turned on. Switching transistor 38 switches low and switching transistor 40 switches high. With switching transistor 38 being low, less current flows through resistor 42 and the current! ! 1rA20 will be low, thus reducing unnecessary power consumption. Output 16
Since the wIF I source 20 is driving a small It current when I is low, subsequent low to high switching is not impeded by J to the I source. Furthermore, the switching transistor 40
being high causes more current to flow through resistor 44, causing the matrix output of node 16 to be quickly pulled to a high logic level at the proper time.

Accordingly, the present invention provides the technical advantage of faster switching in both directions, from high to low and from low to high, while reducing unnecessary power consumption.

Although this invention has been described in terms of bipolar technology, 0 MO
Other techniques such as 8 may also be used.

Although the invention has been described in detail, it should be understood that various modifications may be made within the scope of the invention as defined by the claims.

In addition to the above description, this invention further has the following embodiments.

(1) Multiple fi! ill, and a fast switching logic array having outputs operable to produce high and low logic states, coupled to said M-wheel and producing a current through said live wire. W18 can act like this! A circuit having a generated tiiJ path and a control circuit operable to control the generated 'W1 current in response to an output logic state.

(2) In the path described in mXQ, a control circuit is coupled to the current generating circuit and increases the current generated by the current generating circuit in response to a first logic state; , tli in response to the second logic state
A circuit comprised of circuits capable of reducing the current generated by the current a circuit.

(3) In the lul path described in (1),
a sensing circuit coupled to the output of the memory and operable to detect a state of the output of the memory; and a circuit coupled to the sensing circuit for detecting the current generated by the current generating circuit. A circuit consisting of a blue switching control circuit that acts on the blue.

(4) In the circuit described in paragraph (1), the current generating circuit comprises a diode whose anode is coupled to the switching circuit and whose cathode is coupled to ground and is operable to set the voltage level; and a plurality of transistors operable to generate N currents in response to said voltage level.

(5) In the circuit described in paragraph (3), the sensing circuit is comprised of a differential transistor pair coupled to the output of the memory and to the output of the switching circuit.

(6) In the circuit described in paragraph (5), the differential pair includes a first
NPNJil knowledge transistor with an emitter coupled to the current source and a base Q! a second NPN sense transistor coupled to a voltage and having a collector coupled to the switching circuit.

(7) In the circuit described in paragraph (6), the sensing circuit further includes a first resistor coupled between the collector of the sensing transistor of fRl and the voltage source vs, and the collector of the second sensing transistor. and a second resistor coupled between Vs and Vs.

(8) In the circuit described in paragraph (3), the switching circuit has an emitter coupled to the current generating circuit, a base coupled to the second sensing transistor, and a collector coupled to the current generating circuit.
a first NPN sense transistor coupled to c and a second NPN sense transistor whose emitter is coupled to the output of the memory, whose base is coupled to the collector of the first sense transistor, and whose collector is coupled to vcc. The circuit that is configured.

(9) In the circuit described in (8), the switching circuit further includes a first resistor coupled between the emitter of the first switching transistor and the wA pole of the diode of the current generating circuit; a second resistor coupled between the emitters of the two switching transistors and the output of the memory.

(10) In a method for fast switching of a logic array having a plurality of live wires and outputs operable to generate high and low logic states, sensing the logic state of the output and detecting the sensed state. controlling a current through the IM in response to the IM.

(11) In the method described in section (1G), il
l III includes increasing the N current through the M wire when the output is in the logic state 1 and decreasing the II current through the live wire when the output is in the second logic state. Method.

(12) The method described in paragraph (1G), wherein the sensing step includes comparing the output state of the memory with a constant M quasi-voltage.

(13) In the method described in paragraph (12), the comparing step uses the output to drive a first sensing transistor of a differential pair, and uses a reference voltage to drive a second sensing transistor of a differential pair. 6, when the output of the memory is in a high logic state, the first sensing transistor is turned off and the second sensing transistor is turned on;
The method includes the step of causing a first sense transistor to turn on and a second sense transistor to turn off when the output of the memory is in a low logic state.

(14) In the method described in (10), the first
a logic state is a high logic state and a second logic state is a low logic state.

(15) In the method described in item (1G), the controlling step includes the step of υIm the IF current source using a switching transistor.

(16) In the method described in (10), the second
raising am in response to the logic state of ].

(17) The method of paragraph (16), wherein the pulling step includes switching high a switching transistor coupled to a live wire and a voltage source.

(18) The memory device [(10) predicts the next state of the output of the memory device (12) and responds to the output of the memory by
It has sensing and control circuits (24 and 26) to turn on and turn off the a source (20), making the switching of outputs faster.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional fixed memory device, and FIG. 2 is a circuit diagram of a fixed memory vtW1 using the speed increasing circuit of the present invention.
Figure 3 is a flowchart showing the logic of the present invention, and Figure 4 is a circuit diagram of a preferred embodiment of the present invention. Explanation of main symbols 16: Output node 20: m current source 26: Current switching circuit PLl-PLN: Ml!

Claims (2)

[Claims] (1) In a circuit for fast switching of a logic array having a plurality of product lines and outputs operable to generate high and low logic states, the product line is A circuit having a current generation circuit operable to generate a current through a line and a control circuit operable to control the generated current in response to an output logic state. (2) In a method for fast switching of a logic array having a plurality of product lines and outputs capable of producing high and low logic states, the logic state of the output is sensed and the sensed state is A method comprising the step of responsively controlling a current through the stack.