KR910005499B1 - Apparatus for interfacing channels between isdn exchanger and subscribers - Google Patents

Abstract

The apparatus modulates the (2B+D+C) channel information with 160kpbs into the data stream (DST) with 2.048kbps, divides and processes each channel information, and transmittes the information to a synchronous circuit unit and a CPU. The channel information transmitted from each units are inserted with 2.048 Mpbs and are modulated into U-interface frame structure to transmit through U- interface lines of the private branch exchange side. The apparatus includes an U- tranceiver (6) for converting the system data into the line data and for generating the synchronous clock pulse and the frame pulse, a channel divider (7) for dividing the 2B+D+C channel information into 2B, D and C channel information and for transmitting the divided data by inserting into the DSTi bus data.

Description

Switch-side U interface channel device of small ISDN subscriber concentrator

Figure 1 is a schematic diagram applied in the IMUX / COT system of the present invention.

2 is a block diagram of the present invention.

3A is a frame format diagram on a U interface line.

3B is a timing relationship diagram between a system clock and a 2.048 Mbps data stream.

3C is a biphasic line code diagram used in the present invention.

4 is a timing diagram of used timing signals of the present invention.

* Explanation of symbols for main parts of the drawings

5: hybrid circuit 6: U transceiver

7: Channel separator 8: D channel controller

10: C channel extractor 9: timing generating circuit

11: A bit register 12: M bit register

14: C channel inserter 15: interrupt control circuit

16 Address Decoder 17 Transmit C-Channel Multiframe Generator

18: Receive C channel multiframe synchronization circuit

19: alarm

The present invention relates to a U interface channel device, and more particularly, to a U interface channel device used in an IMUX system.

The IMUX system is a small ISDN subscriber concentrator that has the ISDN service access transmission function of CCITT and aggregates up to 4 ISDN subscribers to transmit through 4 wire metallic lines.

IMUX system is largely composed of IMUX / RT and IMUX / COT. IMUX / RT is subscriber side access device and IMUX / COT is exchange side access device.

The present invention forms part of the IMUX / COT system, which interrupts the switch-side U interface line and transmits (2B + D + C) channel information with a transmission rate of 160 Kbps to a data stream having a transmission rate of 2.048 Mbps (hereinafter referred to as DST). The purpose is to separate and process each channel information and export it to the relevant device (synchronous circuit device, central processing device).

Another object of the present invention is to insert channel information from each device into a 2.048 Mbps stream, convert it into a switch-side U interface frame having a transmission rate of 160 Kbps, and transmit the same to the switch-side U interface line through an encoding process.

It is still another object of the present invention to send a clock and a synchronization signal extracted in each basic access to the synchronization circuit device.

In order to achieve the above object, the present invention provides a hybrid circuit, a U transceiver, a channel separator, a D channel controller, a C channel extractor, an A bit register, an M bit register, a transmitter C channel multiframe generator, a C channel inserter, a timing generator circuit, It consists of a receiving C channel multiframe synchronization circuit, an alarm, an address decoder, and an interrupt control circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of the invention (UCU) applied to an IMUX / COT system, in which 1 is a U interface channel device, 2 is a power supply device, 3 is a synchronization circuit device, and 4 is a central processing unit. Represent each of

(2B + D + C) channel information coming through the U interface 2-line connected to the exchange is divided into 2B channel information and D + C channel information through the U interface channel device 1 (hereinafter referred to as UCU). The channel information is supplied to the synchronous circuit device (SNU) 3, and the (D + C) channel information is supplied to the CPU 4.

및 4.048KHz 클럭신호를 동기회로장치(3)로 2B채널정보와 함께 보낸다. 또한 U인터페이스 선로와는 동기가 벗어났을 경우 이를 상기 동기회로장치(3)에 알려주기 위해 아웃오브 프레임

신호로 보낸다. 제1도에서 전원공급장치(PSU)(2)는 UCU(1)에 필요한 +5V의 전원을 공급할 뿐 아니라, 교환기측에 의한 통신기동에 필나 라이센싱 기능을 갖고 있다.At this time, since the UCU 1 operates as a slave to the switching center, a signal necessary for synchronizing with the system is a frame clock signal of 8 KHz.

And a 4.048 KHz clock signal to the synchronous circuit device 3 together with 2B channel information. In addition, the out-of-frame to notify the synchronization circuit device 3 when the synchronization with the U interface line is out of sync.

To signal. In FIG. 1, the power supply unit (PSU) 2 not only supplies + 5V power required for the UCU 1, but also has a fill or licensing function for communication start by the exchange side.

2 is a block diagram specifically showing the configuration of the present invention. Referring to Figures 2 to 4 will be described the configuration and operation of the present invention.

The hybrid circuit 5 separates and transmits and receives information transmitted and received through two two-wire lines connected to the switching center.

In the present invention, the hybrid circuit 5 is configured by using a resistor, a capacitance, and a coupling transformer, and the transformer is coupled to the line with a 2: 1, and the center is placed on the secondary side so that a direct current between the line and the device is obtained. Electrical coupling was possible.

The U transceiver 6 is a device for writing for the basic access interface of the ISDN. As recommended by the CCITT, it provides a “2B + D” channel format (B channel at 2 × 64 Kbps transmission rate and D channel at 1 × 16 × bks transmission rate) over two wires.

FIG. 3A shows the frame format (160 Kbps) on the U interface line, and FIG. 3B shows the timing relationship between the system clock and the 2.048MH data stream (DST).

The basic access interface of the U transceiver 6 is constituted by a circuit which receives a composite transmission / reception signal coming from a line and a circuit which sends a transmission signal on the line.

The line code used here is a biphase code of FIG. 3C, and the scrambled NRZ data is automatically encoded.

The main reasons for using biphasic line code are as follows.

① The power density is concentrated in the spectrum area to minimize the blocking and dispersion. ② It can shorten the line response and reduce the intersymbol interference which is very important for adaptive echo cancellation. ③ It facilitates clock extraction at the receiving end. ④ Since there is no D.C component in the code, Phantom power supply can be applied without affecting the data. ⑤ It is bipolar signal, so it is easy to receive data and high S / N ratio.

As described above, the line data having a transmission rate of 160 Kbps is converted into an ST bus format of 2.048 Mbps by the U transceiver 6, and the ST bus format coming from the system is converted into line data. The U transceiver 6 is also equipped with a crystal oscillator (X-TAL) to operate in a solvate mode for the master mode of the switching center.

The channel separator 7 separates the " 2B + D + C " channel information (DSTO bus information) input by the ST bus format into 2B, D, and C channel information, respectively, and the 2B channel is connected to the synchronization circuit device 3. The D channel is sent to the D channel controller 8. In addition, the B channel received from the synchronous circuit device 3 and the D channel from the D channel controller are inserted into the DSTi bus.

In the present invention, the channel separation buffer is implemented to perform such a function.

The D-channel controller 8 stores the D-channel, which has entered through the channel separator 7, in a register, and sends an interrupt signal to the CPU to wait for a response from the CPU.

When the CPU detects this signal and sends a control signal, it reads the information in the register of the D-channel controller.

The registers of the D-channel controller 8 must be left in the initial state after the power is applied or the reset operation is performed. The state of each register is controlled by software, and the registers necessary for initial state determination are TCR (Timing Control Register), CR (Control Register), and CCR (C Channel Control Register). The registers used for this purpose are: FIFO Status Register (FSR), Receiver Data Register (RDR), Transmitter Data Register (TDR), Receiver Address Register (RAR), Interrupt Flag Register (IRF), Interrupt Enable Register (IER), and GSR (Interrupt Enable Register). General status register) and CSR (C channel status register).

The U transceiver 6 supplies clock pulses of C4 (4.096 MHz) and FO (8 KHz) to the D channel controller 8 and the timing generating circuit 9, and the D channel controller 8 supplies the clock pulse and It operates in synchronization with the frame clock pulse.

The C channel extractor 10 receives the C channel information separated by the channel separator 7, extracts the A1-A4 bits and the M0-M6 bits of the C channel information by flip-flops, and then registers the corresponding registers (ABR (11)). In step 13, the detection is reported to the CPU (13). Here, A1-A4 bits are control bits with start / stop, test loop and feed control functions, and M1-M6 bits are supervisory channel bits.

The ABR (A bit register) 11 and the MBR (M bit register) 12 are registers having a function of receiving and storing the A bits and the M bits, respectively, and the stored data is sent to or sent from the CPU. The data may be received, stored, and sent to the C-channel inserter 14.

Here, the interconnection between the D-channel information of the D-channel controller 8 and the CPU of the C-channel information already mentioned above is collectively controlled by the address decoder 16 and the interrupt controller 15.

The C-channel inserter 14 receives the A1-A4 and M0-M6 bits from the ABR, MBR registers 11 and 12, and transmits the C channel together with the frame pattern signal from the transmitting C-channel multiframe generator 17. It is inserted into the bit (C7 bit) position and sent to the channel separator 7, and the channel separator 7 inserts mutual signals into the DSTi bus channel as follows.

MBA-A1-A2-A3-A4-M0-M1-M2-M3-M4-M5-M6 where MAB is a multi-frame array bit.

The transmitter C-channel multiframe generator 17 generates a transmission multiframe pulse by counting C3 bit clocks of the C channel information by 12 counters. This pulse is made into a 1.0 signal pattern and sent to the C-channel inserter 14.

The C-channel multiframe synchronization circuit 18 finds the C-channel multiframe synchronization signal from the received C-channel bit RxHK coming from the C-channel extractor 10. By comparing the 1.0 pattern by the multi-frame signal generated in the 12 counters and the received C channel bit (RxHK), the counter clocks are removed one by one if they do not match.

Therefore, the C channel is shifted bit by bit to continue comparison. If it is matched for 4 consecutive frames, it is determined that synchronization is achieved and the IFC signal is output in the 'H' state.

Once in multiframe sync, it is not asynchronous unless multiframe loss continues for more than two frames. However, if the synchronization is lost, the IFC signal is sent to the alarm 19, the ABR 11, and the MBR 12 in the 'L' state to notify the status through the alarm 19 and disable the register.

을 가지고 보드내에서 각각 필요한 각종 타이밍 및 클럭을 발생한다. 다음은 채널과 관련된 각종 타이밍 클럭 신호들에 대한 내용이며, 타이밍 신호들간의 상호 관련은 제4도에 도시되어 있다.The timing generating circuit 9 includes clocks extracted from the U transceiver 6.

Generate various timings and clocks on board. The following is a description of the various timing clock signals associated with the channel, and the correlation between the timing signals is shown in FIG.

Timing signal type Signal name and description

B-채널(B10-B17, B20-B27 비트) 인에이블 신호

B-channel (B10-B17, B20-B27 bits) enable signal

CH-1(C0-C7비트)인에이블 신호

CH-1 (C0-C7 bits) enable signal

C-채널(D0-D1비트)인에이블 신호

C-channel (D0-D1 bits) enable signal

BCKr receive B-channel (B10-B17, B20-B27 bits) clock

CCKr receive CH-1 (C0-C7 bit) clock

DCKr receive D-channel (D0-D1 bit) clock

C0CKr Receive C0 Bit Clock

C3CKr Receive C3 Bit Clock

C7CKr receive C7 bit clock

C7비트 로드신호

C7 bit load signal

CCKx Transmit CH-1 (C0-C7 bit) clock

C0-C6비트 인에이블 신호

C0-C6 bit enable signal

C0-C6비트 로드신호

C0-C6 bit load signal

D-채널(D0-D1비트), C0-C6비트 인에이블 신호

D-channel (D0-D1 bit), C0-C6 bit enable signal

C3CKx Transmit C-Channel (C3 Bit) Clock

LCKr Receive A / M Bit Latch Clock

송신 C-채널(C7비트)로드신호

Transmit C-channel (C7 bit) load signal

The alarm 19 detects the CO bit of channel 1 on the DSTO bus and provides a U-frame locked state. On the other hand, when the received C-channel multiframe is lost, the IFC output goes to 'L' state to display an alarm.

The interrupt control circuit 15 is connected to the address decoder 16, the C channel extractor 10, and the D channel controller 8, and sends an interrupt signal for transmission and reception with the CPU.

The address decoder 16 uses the address signals A1-A6, the chip select signal CS, and the R / W signal necessary for the transmission and reception of the ABR 11, the MBR 12, and the CPU, respectively, to obtain timing signals respectively. Make it up

The mode selection and reset circuit 20 determines the mode to operate the U transceiver 6 normally. For this purpose, it operates in the slave mode so that # 001 is input to M0-M1 of the U transceiver 6. There is a function of preventing the malfunction of the U transceiver 6 at power on and resetting the initial state of the D-channel controller 8.

The present invention configured as described above forms a part of the IMUX / COT system, and terminates the U interface and converts the channel information of " 2B + D + C " channel having a transmission rate of 160 Kbps into a data stream having a transmission rate of 2.048 MHz. The information is separated and processed, and the channel information from each other device is inserted into the data stream bus, converted into a U interface frame type having a transmission rate of 160 Kbps, and transmitted through the encoding process to the U interface line. The synchronization signal with the clock extracted from the basic access can be supplied to the synchronization circuit device.

Claims (1)

The hybrid circuit 5 and the hybrid circuit 5 for converting information transmitted through a two-line line into a transmission / reception signal, and convert the line data into system data or convert data from the system into line data. , Synchronous clock pulse

And frame pulse

U transceiver 6, which is connected to the U transceiver 6, generates DSTP bus data, '2B + D + C' channel information from the U transceiver 6, into 2B, D, and C channels. It is connected to the channel separator 7 and the channel separator 7 for respectively separating or inserting the separated data into DSTi bus data entering the U transceiver 6, and having registers to interconnect with the CPU. A D-channel controller 8 for transmitting and receiving D-channel information, a C-channel extractor 10 connected to the channel separator 7 and having flip-flops to extract only a corresponding control bit from the separated C-channel information; A bit register (ABR) connected to the C channel extractor 10 for designating the data to send or receive the control bits used for start / stop, test loop and feed control to or from the CPU. 11), C It is connected to the null extractor 10, M bit register (MBR) 12 for storing and storing the data once to receive the monitoring control bit from the CPU, C3 bit clock of the C channel information by the counter 12 Transmit C-channel multi-frame generator 17, the A-bit register 11, M-bit register 12, transmit C-channel multi-frame generator 17, and channel separator 7 for counting and generating transmit multi-frame pulses. A C channel inserter 14 for sending C channel information to the channel separator 7 for insertion into a DSTi bus and a timing generator for providing a timing signal necessary for connecting to the U transceiver 6. A C-channel multi-frame synchronous circuit 18 connected to the circuit 9, the ABR 11, the MBR 12, the C-channel extractor 10, and the timing generating circuit 9 to check the frame synchronous / asynchronous state. The timing generation circuit 9 and the C-channel mulch. Alarm 19 connected to frame sync circuit 18 to indicate synchronous / asynchronous status, CPU connected to ABR 11 and MBR 12 to select corresponding register for transmission and reception with CPU And an interrupt control circuit 15 connected to the decoder 16, the address decoder 16, the C channel extractor 10 and the D channel controller 8 to send an interrupt signal to the CPU for transmission and reception with the CPU. U interface channel device characterized in that.

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