KR920001550B1 - Apparatus for interfacing between multiplexer and end-user terminal - Google Patents

Abstract

A hybrid circuit (5) interconnects four lines having separate receiving/transmitting lines, and an A-bit register (11) temporarily stores the received data before sending or receiving control bits to or from a CPU. A C channel multi-frame synchronizing circuit (10) checks the synchronized or non-synchronized state of the frame, and a warning detecting circuit (19) displays the synchronized or non-synchronized state of the frame. An address decoder (16) selects a relevant register for communicating with the CPU, and an interrupt control circuit (15) sends an interrupt signal to the CPU to effect a communication with the CPU.

Description

U interface channel device

1 is a schematic diagram showing the operation in the PMUX / COT system of the present invention.

2 is a block diagram showing the configuration of the present invention.

Figure 3a is a 16Kbps signal frame format diagram on a U interface line.

3b is a timing relationship diagram between a system clock and a 2.048 Mbps data stream.

3C is a bi-face coded diagram.

4 is a correlation diagram of timing signals generated by a timing generation circuit.

* Explanation of symbols for main parts of the drawings

6: U transceiver 7: Channel separator

8: C channel extractor 9: timing generator

10: C-channel multiframe synchronous circuit 11: A bit register

12: M bit register 13: U transceiver operation control register

14: C channel inserter 15: interrupt control circuit

16 Address Decoder 17 Transmit C-Channel Multiframe Generator

19: alarm detection circuit 20: mode selection circuit

The present invention relates to a U interface channel device, and more particularly, to a U interface channel device used in a primary multiplexer (PMUX) system.

The PMUX system applies the established inter-station transmission technology to the subscriber network, multiplies 10 or 12 ISDN basic access subscribers scattered in groups at remote locations at the bit rate of DS1 to the ISDN exchange. It is a kind of ISDN subscriber multi-device that connects. Especially, it was developed to provide efficient and economical ISDN service to existing subscribers in the area where ISDN exchange is not installed at the early stage of ISDN introduction by using existing DS1 transmission system.

Typical application configuration of PMUX system can be PMUX / PT and PMUX / COT. PMUX / RT is for connection with subscriber side interface line and PMUX / COT is for connection with exchange side interface line.

The present invention forms a part of the PMUX / COT system, and terminates the switch-side U interface line, converts ″ 2B + D + C ″ channel information at 160 Kbps into a data stream (DST) at 2.048 Mbps and provides each channel information. Process the data, send it to the corresponding device (synchronous circuit device, CPU), insert channel information from each device into 2.048-Kbps stream, convert it to 160Kbps switch-side U interface frame type, The purpose is to transmit.

The present invention, in order to achieve the above object, in the U interface channel apparatus of the PMUX system for providing ISDN service using a DS1 class transmission equipment, a two-wire line connected to the switching center and a four-line line separated from the transmission and reception signal lines Interconnecting hybrid circuits; A U transceiver connected to the hybrid circuit and converting the line data into system data or converting data from the system into line data and oscillating a synchronous clock pulse and a frame pulse; The ″ 2B + D + C ″ channel information, which is connected to the U transceiver and is DSTo bus data from the U transceiver, into ″ 2B + D ″ and ″ C ″ channels, respectively, or the separated channel information is divided into A channel separator for inserting DSTi bus data into the transceiver; A C channel extractor connected to the channel separator and including flip-flops to extract only a corresponding control bit of the separated C channel information; An A bit register coupled to the C channel extractor and storing the data once for sending to or receiving control bits from the CPU for start / stop, test loop and feed control; An M bit register coupled to the C channel extractor and storing the data once for receiving monitoring control bits from a CPU; A U transceiver operation control register for allowing a CPU to access a CR (control register) and a DR (diagnostic register) which are internal registers of the U transceiver; A transmission C-channel multiframe generator for generating a transmission multiframe pulse by counting a C3 bit clock of the C channel information by a counter 12; A C-channel inserter connected to the A-bit register, the M-bit register, the transmitting C-channel multiframe generator, and the channel separator to send the input C-channel information to the channel separator to insert into the DSTi bus; A timing generating circuit connected to said U transceiver and providing a timing signal necessary therein; A C-channel multi-frame synchronous circuit connected to the A-bit register, M-bit register, C-channel extractor and timing generator 9 to check frame synchronization / asynchronous state; An alarm detection circuit coupled to the timing generation circuit and the C-channel multiframe synchronization circuit for displaying a synchronous / asynchronous state; An address decoder connected to a CPU, the A bit register, an M bit register, and an operation control register to select a corresponding register for transmission and reception with the CPU; And an interrupt control circuit connected to the address decoder and the C channel extractor to send an interrupt signal to the CPU for transmission and reception with the CPU.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a schematic diagram showing an application in PMUX / COT of the present invention.

The PMUX / COT U interface channel device 1 terminates the switch-side U interface line and accommodates ISDN basic access (2B + D).

The channel information of the 2.048Mbps DST bus structure is extracted from the exchange side U interface frame format having a 160Kbps line speed and inserted in the reverse direction. This separated 2B + D channel is sent to the SUN (synchronous circuit unit) 3. The 2B + D channel from the top is inserted on the ST bus from SUN (3) and returned to the U interface channel device (1).

The C channel on the U interface contains maintenance related information, which is first extracted from the U interface channel device 1 and interrupted by the CPU.

Each of the clocks F0 and C4 extracted from each basic access is sent to the SUN 3 together with the synchronization signals OF1-OF4.

The power supply unit 2 (PSU) not only supplies the + 5V power required for the UCU 1 but also has the necessary line sensing function of the U interface line.

2 is a block diagram of the present invention, FIG. 3a is a 160 Kbps signal frame structure on a U interface line, FIG. 3b is a timing relationship diagram between a system clock and a 2.048 Mbps data stream, and FIG. 3c is a biphasic coded diagram. Fig. Is a correlation diagram of timing signals generated by the timing generation circuit.

Referring to Figures 2 to 4 will be described the configuration and operation of the present invention.

The hybrid circuit 5 transmits a 160Kbps signal coming in through a two-wire line (2W) (i.e., a U interface line) connected to an switching center through a four-line line (i.e., a line having separate transmission and reception signal lines) to the U transceiver 6 It transmits the signal of 160Kbps transmitted from U transceiver through 4 line and converts it to 2 line (2W). In the present invention, the hybrid circuit 5 is configured using a resistor, a capacitance, and a coupling transistor, and the transformer has a turns ratio of 2: 1, and a center tab is provided on the secondary side to provide a line and Direct current and electrical coupling between the devices was possible.

That is, direct current electricity (PF + PF-) can be supplied from the exchange station through the center tap of the 2-wire line.

The U transceiver 6 is a device for writing for the basic access interface of the ISDN. As recommended by the CCITT, it provides a ″ 2B + D ″ channel structure (B channel of 2 × 64 Kbps rate and D channel of 1 × 16Kbps rate) over a two-wire line.

The basic access interface of the U transceiver 6 is a circuit for receiving an encoded transmission line signal of 160 Kbps speed (see FIG. 3C) coming from the line through the hybrid circuit 5 and reproducing the NRZ data (see also FIG. 3C). And a circuit for biphasically coding the NRZ data to be transmitted (see also FIG. 3C) and transmitting a 160 Kbps transmission line signal (see also FIG. 3C). The line code used here is the biphase code of Figure 3c, and the NRZ data is scrambled and differentially encoded (see Figure 3c).

The main reasons for using biphasic line code are as follows.

First, the power density is concentrated in the spectrum region, which minimizes blocking and dispersion. Second, it can shorten the line response and reduce the intersymbol interference which is very important for adaptive echo cancellation. Third, it facilitates clock extraction at the receiving end. Fourth, since there is no direct current (D.C) component in the code, phantom power supply can be applied without affecting the data. Fifth, since it is a bipolar signal, data reception is easy and signal-to-noise ratio (S / N) ratio is high.

신호는 8㎑ 주기의 프레임 신호이며, LOUT 신호는 160Kbps 속도를 갖는 데이타이고, 1비트의 프레임(F)비트, 1비트의 C채널, 2비트의 D채널(D0,D1), 16비트의 B채널(B10,B11,……,B17,B20,B21,……,B27) 비트로 되어있어 총 20비트를 이루고 있다.As described above, the line data having a transmission rate of 160 Kbps is converted into a data stream of 2.048 Mbps as shown in FIG. 3b after reproducing data having the same structure as the LOUT signal of FIG. 3a by the U transceiver 6. In Figures 3a and 3b

The signal is a frame signal of 8 ms period, and the LOUT signal is data having a speed of 160 Kbps, one bit of frame (F), one bit of C channel, two bits of D channel (D0, D1), and 16 bits of B. The channel (B10, B11, ..., ..., B17, B20, B21, ..., ..., B27) bits make up a total of 20 bits.

신호는 8㎑ 주기의 프레임 신호로 데이타의 시작점을 인식하도록 하며,

신호와 C2 신호는 4.096㎒ 및 2.048㎒ 속도의 클럭신호로 데이타 비트를 인식하는데 쓰인다.In Figure 3b

The signal is to recognize the starting point of the data as a frame signal of 8㎑ period,

The signal and the C2 signal are used to recognize data bits as clock signals at 4.096 MHz and 2.048 MHz speeds.

The 2.048Mbps data stream contains 32 channels of 8 bits in one channel, and the first channel is CHO.

The 2.048 Mbps data stream has the same structure as the DST signal of FIG. 4, the first two bits are assigned D0 and D1 in the CHO of the first channel, the C channels (C0… C7) are allocated to the second channel, and the third channel. Channel B is assigned to channel 4 and channel 4, respectively. And the 5th to 32nd channels are left blank.

As described above, the line data having a transmission rate of 160 Kbps is converted into an ST bus structure of 2.048 Mbps by the U transceiver 6 and transmitted as a DSTo signal to the channel separation circuit 7.

On the contrary, it receives the DSTi signal, which is the input DST bus from the channel separation circuit 7, converts it into the line data of 160Kbps transmission rate and sends it to the hybrid circuit 5.

In addition, the U transceiver 6 is provided with a 10.24 MHz crystal oscillator oscillating circuit for operating in the slave mode to the master mode of the switching center.

That is, the U transceiver 6 extracts timing information from the received signal information of the U interface line 2W coming from the switching center, and synchronization is formed, and phase synchronization is performed with a 10.24 MHz clock.

The channel separation circuit 7 is a STi signal that separates two B channels and two bits of D channels from the DS transceiver bus from the U transceiver 6 and includes ″ 2B + D ″. Send to). Also, 2B channel and D channel are inserted into DSTi bus to STo signal received from SUN (3).

The channel separator 7 separates the transmission C channel from the DSTo and sends it to the C channel extractor 8, and receives the received C channel from the C channel inserter 14 and loads it on the DSTi bus.

The C channel extractor 8 receives the C channel information separated by the channel separator 7, extracts the A1-A4 bits and the M0-M6 bits of the C channel information by flip-flops, and then registers the corresponding registers (ABR (11), After sending to MBR 12, the CPU can read the detected information.

Here, A1-A4 bits are control bits having start / stop, test loop and feed control information, and M0-M6 bits are information bits for monitoring channel.

The ABR (A bit register) 11 and the MBR (M bit register) 12 are registers having a function of receiving and storing the A and M bits, respectively, and the received data can be read if the CPU desires it. In other words, the transmission data is directly received from the CPU, stored, and sent to the C-channel inserter 14.

The CPU and the interchange of the C channel information are collectively controlled by the address decoder 16 and the interrupt controller 15.

The C-channel inserter 14 receives the A1-A4 and M0-M6 bits from the ABR, MBR registers 11 and 12, and the frame pattern signal MAB from the transmit C-channel multiframe generator 17. Together with the channel separator 7, the channel separator 7 sends the signal to the remote station via the U transceiver 6 to confirm the performance of the C channel information. In this case, the order of insertion into the DSTi bus channel is as follows.

″ MAB-A1-A2-A3-A4-M0-M1-M2-M3-M4-M5-M6 ″

Here, MAB is a multi-frame array bit, has a pattern ″ 1010 ″ and is used to recognize information in the C channel.

Although the C channel information consists of 12 bits in total, the actual C channel allocated to 160Kbps transmission rate data is 1 bit of the BKbps rate.

To solve this problem, 12-bit C-channel information is distributed at a rate of 0.667 Kbps and inserted into a 1-bit C-channel position of 8 Kbps in a multi-frame format and transmitted.

The transmission C-channel multiframe generator 17 generates a transmission multiframe pulse by counting a C3 bit clock of the C channel information by 12 counters. This pulse is made into a signal pattern of 1,0 and sent to the C-channel inserter 14.

In the DST bus structure, the transmit C channel bits are allocated C3 bits, and the receive C channel bits are allocated C7 bits.

The receiving C-channel multiframe synchronizing circuit 10 finds the C-channel multiframe synchronizing signal from the receiving C-channel information RxHK coming from the C-channel extractor 8.

That is, the C channel information can be recognized by finding the received MAB bit. The reception C-channel multiframe synchronization circuit 10 compares the 1,0 pattern of the multiframe signal generated by the 12 counters and the reception channel bits RxHK and removes the counter clocks one by one if they do not match.

Therefore, the C channel is shifted by one bit to continue comparison.

If four multi-frames match in succession, it is determined that synchronization has been performed and the IFC signal is output in a high ″ H ″ state. Once in multiframe sync, it will not be asynchronous unless multiframe loss continues for more than 2 multiframes. However, if synchronization is lost, the IFC signal is sent low (″ L ″) to the alarms 19, ABR 11, and MBR 12 to notify the CPU of the status through the alarm 19 and simultaneously register the register. Let it be. This is to prevent the CPU from reading because the C channel information is an invalid bit when an alarm occurs.

)을 가지고 장치내에서 각각 필요한 각종 타이밍 및 클럭 신호들(제4도 참조)을 발생한다.The timing generating circuit 9 includes clocks extracted from the U transceiver 6.

And generate various necessary timing and clock signals (see Fig. 4) in the device.

The following is a description of the various timing and clock signals associated with the channel, and the correlation of each timing signal is shown in FIG.

)를 시작점으로 하여 첫번째 채널의 D0 및 D1 비트가 위치한다. 다음 두번째 채널에는 C채널이 할당되며 C0-C7비트로 이루어지고, 실제 쓰이는 C채널 정보비트는 송신 C채널 용으로 C7비트, 수신 C채널용으로 C3비트가 쓰인다.In FIG. 4, the DST bus signal has a speed of 2.048 Mbps in which one cycle of the 2.048 MHz clock signal C2 is 1 bit, and the allocated information bit is an 8 ms frame signal (

), The D0 and D1 bits of the first channel are located. The second channel is allocated C channel and consists of C0-C7 bits, and the actual C channel information bits are C7 bits for the transmitting C channel and C3 bits for the receiving C channel.

The next 3rd and 4th channels are assigned B channels (B10-B17, B20-B27 bits), respectively.

신호는 D채널(D0-D1비트) 인에이블 신호로 채널분리기(7)에서 로우(″L″)상태일 경우 DSTo 버스에 D채널을 삽입하는데 쓰인다.

The signal is a D-channel (D0-D1 bit) enable signal that is used to insert the D-channel into the DSTo bus when it is low (″ L ″) in the channel separator 7.

신호는 C채널(C0-C7비트) 인에이블신호이며 채널분리기(7)에서 로우(″L″)상태 일 경우 DSTi 버스에 C0-C7비트 삽입을 수행하는데 쓰인다.

The signal is a C-channel (C0-C7-bit) enable signal and is used to perform C0-C7-bit insertion into the DSTi bus when it is low (″ L ″) in the channel separator 7.

신호는 B채널 인에이블 신호로 채널분리기(7)에서 로우(″L″)상태일 경우 DSTo 버스에 B채널의 삽입을 수행하는데 쓰인다.

The signal is a B-channel enable signal, which is used to perform the insertion of the B-channel into the DSTo bus when the channel separator 7 is low (″ L ″).

The BCKr clock signal is used to separate the B channel on the DSTi bus in the channel separator 7 with the received B channel clock.

The CCKr clock signal is used to separate the C0-C7 bits from DSTo in the channel separator 7 and insert the C0-C7 bits into the DSTi as the received C-channel (C0-C7) clock.

The DCKr clock signal is used to separate the D0-D1 bits from the DSTi in the channel separator 7 as a receive D-channel (D0-D1 bit) clock.

The COCKr is used to extract the C0 bit on the DSTo bus from the alarm detection circuit 19 as a receive C0 bit clock.

C3CKr is used to extract the C3 bit on the DSTo bus from the channel separator 7 with the received C3 bit clock.

신호는 C7 비트로드 신호로서 C채널 삽입기(14)에서 송신 C채널 정보를 C7비트 위치에 1비트 형태로 삽입시키는데 쓰인다.

The signal is a C7 bit load signal, which is used by the C channel inserter 14 to insert the transmitted C channel information into the C7 bit position in 1 bit form.

The C7CKx signal is a transmission C7 bit clock signal which is used by the channel separator 7 to insert C7 bits, which are transmission C channel information, on the DSTi bus.

The LCKx clock signal is used when the C-channel inserter 14 receives the transmission A1-A4 and M0-M6 information received from the ABR 11 and the MBR 12.

The clock speed of the LCKx is 0.667µs, a C-channel multiframe rate.

The operation control register 12 (hereinafter referred to as CCR) of the U transceiver 6 allows the CPU to access CR (control register) and DR (diagnosis register), which are internal registers of the U transceiver. When writing data necessary for the operation of the U transceiver via the data bus, LUKx (see Figure 4) is stored in the shift register by a clock signal.

The shift register is then inserted into the C0-C6 bit position of the DSTi bus CH1. If the CPU wants to read the contents of the CCR, it can be read by accessing it through the shift register.

The alarm detection circuit 19 detects the C0 bit of channel 1 on the DSTo bus and provides a U frame synchronization state. This is because the U transceiver 6 outputs the U frame synchronization state on the C0 bit. On the other hand, if the received C-channel multiframe is lost, the IFC output goes low (″ L ″) to enable the alarm display.

The interrupt control circuit 15 generates an interrupt signal and sends it to the CPU when the C channel information bit exists so that the CPU can read the C channel information state detected by the C channel extractor 8.

At this time, when the CPU reads the C channel related register, the address decoder 16 releases the interrupt signal. The address decoder 16 includes an address signal A1-A6, a chip select signal CS, and a read / write signal (R /) necessary for transmission and reception between the ABR 11, the MBR 12, the CCR 13, and the CPU. Each control signal is generated using W).

The mode selection circuit 20 determines the mode so that the U transceiver 6 operates in the slave mode.

The present invention configured as described above forms a part of the PMUX / COT system, and terminates the switch-side U interface and transmits data of ″ 2B + D + C ″ channel information having a transmission rate of 160 Kbps and a transmission rate of 2.048 MHz. It converts each channel information by converting it into a stream, inserts channel information from each other device into a data stream bus, converts it into a U interface frame type having a transmission rate of 160 Kbps, and passes the U interface line through an encoding process. In addition, the synchronization signal with the clock extracted from each basic access can be supplied to the synchronization circuit device. Thus, the present invention has the effect of providing an efficient and economical ISDN service using the existing DS1 class transmission equipment connected to the exchange side interface line.

Claims (3)

In the U interface channel device of the PMUX system for providing ISDN service using a DS1 transmission facility, a hybrid circuit (5) interconnecting a two-wire line (2W) connected to an switching center and a four-line line having separate transmission and reception signal lines (5) ; U transceiver 6, which is connected to the hybrid circuit 5, converts the line data into system data or converts data from the system into line data and generates a synchronous clock pulse C ₄ and a frame pulse F 0. ); And ″ 2B + D ″ and ″ C ″ channels, respectively, which are connected to the U transceiver 6 and which separate DSTo bus data from the U transceiver 6 into ″ 2B + D ″ and ″ C ″ channels. A channel separator (7) for inserting the received channel information into the DSTi bus data entering the U transceiver (6); A C-channel extractor (8) connected to the channel separator (7) and having flip-flops to extract only a corresponding control bit of the separated C-channel information; An A bit register (ABR) 11 connected to the C channel extractor 8 and storing the data once for sending to or receiving control bits from the CPU for use in start / stop, test loops and feed control; An M bit register (MBR) 12 connected to said C channel extractor 8 and storing said data once for receiving monitoring control bits from a CPU; A U transceiver operation control register (13) for allowing a CPU to access CR (control register) and DR (diagnostic register), which are internal registers of the U transceiver (6); A transmission C-channel multiframe generator 17 for generating a transmission multiframe pulse by counting a C3 bit clock of the C channel information by a counter 12; It is connected to the A bit register 11, the M bit register 12, the transmitting C channel multiframe generator 17 and the channel separator 7 to send the input C channel information to the channel separator 7 to the DSTi bus. A C channel inserter 14 for inserting; A timing generation circuit (9) connected to said U transceiver (6), for providing a timing signal necessary therein; A C-channel multiframe synchronization circuit 10 connected to the A bit register 11, the M bit register 12, the C channel extractor 8, and the timing generation circuit 9 to check frame synchronization / asynchronous state; An alarm detection circuit (19) connected to the timing generation circuit (9) and the C-channel multi-frame synchronization circuit (10) for displaying a synchronous / asynchronous state; An address decoder (16) connected to a CPU and the A bit register (11), an M bit register (12), and an operation control register (13), for selecting a corresponding register for transmission and reception with a CPU; And an interrupt control circuit (15) connected to the address decoder (16) and the C channel extractor (8) for sending an interrupt signal to the CPU for transmission and reception with the CPU. The U transceiver 6 is configured to convert data having a transmission speed of 160 Kbps into a ST bus format of 2.048 Mbps, or convert ST bus data of 2.048 Mbps into a transmission speed of 160 Kbps. U interface channel device. The U interface channel device according to claim 1, further comprising a mode selection circuit (20) connected to said U transceiver (6) for switching said U transceiver to operate in a slave mode.

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