KR910005496B1 - Apparatus for common channel control of isdn subscribers - Google Patents

Abstract

The apparatus is for controlling channel assignment. The apparatus condenses 8-B channels into 5-B channels and divides the D- channelof the communication line. The transmission speed of 2.048kbps is converted into 400 kbps in the apparatus. The apparatus includes an a-channel extracting/inserting unit (9) for extracting the a-channel from the received line data and for inserting the a-channel transmitted from the CPU into the transmission data stream, a D-channel extracting/inserting unit (10) for executing same functions of the a-channel extracting/inserting unit (9) to the D-channel, a receive frame synchronizing unit (11) for extracting frame pattern from the received data and comparing the extracted frame to the self generated reference frame to find the correct position of the frame so that when succesive four frames are coincide, the frame synchonizing signal is transmitted.

Description

Common Channel Control Device in Switching Station Side of Small Subscriber Concentrator

1 is a system diagram showing the application of the present invention to a switching center side station apparatus (COT) of a small subscriber contacting apparatus (IMUX).

2 is a block diagram showing a configuration of the present invention.

3a is a structural diagram of a 2,048 kbps ST-bus data stream.

3b is a 400 kbps line data format diagram.

3C is an exemplary diagram illustrating a TS allocation method of a timeslot (TS) assignment circuit.

4 is a correlation diagram of timing signals generated in a timing generation circuit.

* Explanation of symbols for main parts of the drawings

5 buffer buffer memory circuit 7 channel speed conversion circuit

8: B channel time slot allocation circuit 9: a channel separation / insertion circuit

10: D channel separation / insertion circuit 11: Receive frame synchronization circuit

12: timing signal generating circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common channel control device, and more particularly, to a common channel control device in a switching station side end station device of a small subscriber connection device (hereinafter referred to as IMUX).

The IMUX system is a small ISDN subscriber system that has the ISDN (Integrated Information Communication Network) function of CCITT and collects up to 4 ISDN basic access (＂2B + D＂ channels) subscribers and transmits them through 4-wire metallic lines. The IMUX system is largely composed of IMUX / COT and IMUX / RT. IMUX / COT is a switchboard terminal device, and IMUX / RT is a subscriber terminal device.

The present invention forms a part of the IMUX / COT device, and is located between SNU (synchronous circuit device) and LIU (line interface device) for the purpose of line termination and channel distribution control.

Another object of the present invention is to tangentially connect the 8B channel to the 5B channel and to separately insert the line D channel.

Another object of the present invention is to convert a transmission rate of 2.048kbps to a transmission rate of 400kbps in the system.

In order to achieve the above object, the present invention provides a buffer buffer memory means for temporarily storing data to be transmitted and received in a memory and outputting the data serially or in parallel according to an internal transmission / reception clock and a timing signal. Connected to the buffer buffer memory means for receiving a received frame signal and a write related control signal made in the received clock, a read related control signal made in accordance with the transmitted frame signal and the transmitted clock, and timing signals necessary for parallel / serial and serial / parallel change. A buffer buffer memory control means for supplying a memory means of a buffer buffer, and a channel speed converting means connected to said buffer buffer memory means for converting a data transfer rate. B channel time slot assignment means connected to the channel speed converting means for allocating a time slot of the B channel, and connected to an external line coming into the buffer buffer memory means to separate a channel from the receiving line data, or A channel separation / insertion means for inserting a transmission a channel into the transmission data stream through the external line, a line between the buffer buffer memory means and the channel speed conversion means to separate D channel from received data, or D channel separating / inserting means for inserting into the transmitting data stream into the transmission data stream, connected to an external line coming into the buffer buffer memory means, extracts a frame pattern from the received data, and compares it with a frame generated by itself to find the exact frame position. The frame is compared for four frame periods A receiving frame synchronizing means for outputting a synchronous signal and otherwise outputting an asynchronous signal, a timing signal generating means for generating necessary timing signals inside the apparatus, and a digital phase for receiving a frame clock from the timing signal generating means to generate a system clock Transmission frame inserting means for receiving the frame from the fixed loop means, the timing generating means for generating a transmission frame signal and inserting the transmission frame signal into the external line of the memory means of the buffer buffer; Means, a transmission clock generating means for receiving an existing frame clock to generate an internal clock, a channel timing signal generating means for receiving a receiving frame clock and an internal clock to generate an a channel timing signal, and a system clock for converting the speed Phil in Sudan Consists of a clock to the B channel timing signal generating means for supplying.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing the application of the present invention, FIG. 2 is a block diagram showing the structure of the present invention, FIG. 3A is a structural diagram of a 2.048kbps ST-bus data stream, and FIG. 3B is a 400kbps line data format. 3C is a time slot allocation circuit diagram, and FIG. 4 is a correlation diagram of timing signals.

First, referring to FIG. 2, the common channel device 1 (hereinafter referred to as CCU) in IMUX / COT receives a 4 × 2B channel using a synchronization circuit device (hereinafter referred to as SNU) (2) and a 2.048 kbps ST bus. It tangentially converts to 5B, converts to 400kbps speed, forms a transmission frame pattern, inserts it into the line format along with the a and D channels from the CPU 4, and transfers them to the interface device 3 (hereinafter referred to as LIU). On the contrary, frame synchronization is performed by receiving 400kbps data from the LIU, and once synchronization is performed, all timings are set, and accordingly, a channel is extracted and sent to the CPU 4.

However, 400kbps received D-channel and B-channel data are stored in the buffer memory in accordance with the reception clock and then output in accordance with the internal clock. Here, the D channel is separated and sent to the CPU, and the B channel is converted to the speed at 2.048 kbps and is controlled by the CPU and allocated to the corresponding channel timeslot. In addition, the CCU 1 generates a clock by receiving a reference clock from the synchronous circuit device SNU, and accordingly generates various timings and supplies them to each part and also to other devices.

Next, the configuration of the present invention will be described with reference to FIGS. 2 to 4.

The buffer buffer memory circuit 5 clocks 400 kbps received data in series to 8 bits in parallel by clocking the B / D channel bits except for the F (frame) bit and the a bit, and transfers them to the data input of the memory unit. Create a write address internally and store it in the memory of the corresponding address. Then, the data stored in the address is displayed as the data output of the memory of the address according to the read address, and the data is inputted in parallel by the load signal according to the frame clock, and is output in series according to the 400KHz clock.

The buffer memory control circuit 6 generates a write related control signal of the buffer memory circuit 5 according to the reception frame signal FRBr and the reception clock C400r, and transmits a data read address to the transmission frame F8X and the transmission. Make according to the clock (C400X).

In addition, timing signals for serial / parallel (S / P) and serial / parallel (P / S) conversion are generated.

The channel speed converting circuit 7 performs S / P conversion on the B1-B5 channels of the 2.048 kbps data stream coming from the channel timeslot allocation circuit 8, loads them in the flip-flop circuit, and converts them according to the timing. Output at 400KH output. In addition, B1-B5 channel coming in at 400kbps line speed is S / P-converted in flip-flop circuit and output according to 2 / 048KHz clock.

The B-channel timeslot assignment circuit 8 accepts 4x2B channels coming from the SNU via 2.048kbps input data streams STi1-STi4, condensing only 5B, and assigns only the designated timeslim position of the 2.048kbps output data stream SToO. Assign to Conversely, it is allocated to each designated time slot position of 5B channels STo1-STo4 coming through STiO. Information required for time slot assignment, including aggregation information, is subject to CPU control.

The internal registers of the B-channel timeslot allocation circuit to be accessed to perform this are the control register (CR), the connection memory low (CML), and the connecton memory high (CMH).

The structure of the 2.048 kbps class ST bus data stream is shown in FIG. 3a, the 400 kbps class line data format is shown in FIG. 3b, and the allocation method of the timeslot TS assignment circuit is shown in FIG.

The a channel separating / inserting circuit 9 separates a channel from the 400 kbps receiving line data coming from the LIU, and inserts a sending a channel coming from the CPU into the transmission stream.

The D channel separating / inserting circuit 10 separates the D channel from the received 400 kbps data passing through the buffer memory circuit 5, and inserts the D channel coming from the CPU into the transmitting 400 Kbps data stream through the buffer.

The receiving frame synchronizing circuit 11 extracts a frame pattern from the received 400kbps data and finds the exact position of the frame by comparing it with a frame generated by itself. When four consecutive frame periods are compared and the frame is synchronized, the frame is synchronized. Otherwise, the signal is asynchronous and the LED emits red light. Once synchronized, it will not enter asynchronous state unless there is more than two consecutive frames. In addition, 50 counts of the receive 400KHz (C400r) clock to generate a receive frame (FRBr). Make FRNr into 1010 frame pattern and compare with Rx DATA.

The compared values are inverted to store the values for four frames in the shift register. The comparison value for these four frames is judged by the state, and a synchronization signal (IF / OF) is output. If asynchronous (OF), removes C400r clocks one by one. If this missing clock is written to the frame counter, the position of the FRBr changes. Therefore, if the position of the FRBr and the frame bits included in the received data coincide four times in succession, the synchronization state is entered.

The timing generation circuit 12 generates timing related to the 400 kbps data stream, and generates the B channel timing of the ST bus stream at the 2.048 kbps speed of the speed conversion circuit 7.

The contents of the other timing signals are as follows, and the correlation between the signals is shown in FIG.

F8: 8KHz system frame clock DEn: D-channel enable signal

aEn: a channel enable signal TxDCK: transmit D channel clock

Txack: Transmit a channel clock RxDck: Receive D channel clock

Rxack: Receive a channel clock PLx: Transmit parallel load signal

BEn: B channel enable BCR: Receive B channel clock

The DPLL (Digital Phase Locked Loop) circuit 13 generates the system clocks F0, C4, C2 synchronized with the frame clock F8. That is, it is used to synchronize the 8 KHz frame F0 and the clocks C4 and C2 associated with the ST bus to the internal frame F8. For this purpose, the master clock of the circuit is 16.388 MHz clock.

The transmission frame insertion circuit 14 generates a transmission frame pattern from the frame signal F8 and inserts it into the transmission data stream.

The transmission frame generation circuit 15 generates a transmission frame signal FRBx by counting the clock pulse C400 at a transmission frame counter by 50 counts.

The transmission system clock generation circuit 16 generates the reference clock (RFR) 8KHz supplied from the synchronous circuit device (SNU) using the PLL to transmit 400KHz (C400x) and 800KHz (C800x).

The a-channel timing generation circuit 17 receives the received frame signal FRBr and the received clock signal C400r generated from the received frame synchronization signal 11, and thus a channel control signal, that is, a clock control signal ack. And a enable signal aEn is generated, and these control signals are sent to a channel separation / insertion circuit 9.

The ST bus B-channel timing generation circuit 18 receives the system clocks F0 and C2 to generate the control clocks BCKx and PLr necessary for the speed conversion circuit 7.

The present invention is configured as described above, and transfers 848 channel information of 2.048kbps rate coming from SNU (Synchronous Circuit Device) in IMUX / COT to 5B channel of 2.048kbps rate and transmits a-channel and D-channel information from CPU. It is inserted into the 5B channel information at all times to transmit the frame signal (FR) to the LIU (line interface device), and also separates the kb5B + 4D + a + F ＂channel information of 400kbps from the LIU, and then separates the 4D +. The a channel information is sent to the CPU, and the 5B channel information is allocated among the 8B channels to be sent to the SNU device.

Claims (3)

It is connected to the buffer buffer memory means 5 and the buffer buffer memory means 5 configured to temporarily store data to be transmitted / received in a memory and output the data serially or in parallel according to internal transmission / reception clocks and timing signals. A buffer-buffer memory control means 6 for supplying a write-related control signal and a timing signal for parallel / serial and serial / parallel conversion to the buffer buffer memory means 5 and the buffer buffer memory means 5, respectively. Channel rate converting means (7) for converting the data transmission rate, B channel time slot assigning means (8) for allocating a B channel timeslot and connected to said channel rate converting means (7), and said buffer buffer memory means ( 5) is connected to an external line coming in, and separates a channel from the received line data to insert a channel into the transmission data stream through the external line. A line between the a-channel separating / inserting means 9, the buffer buffer memory means 5, and the channel speed converting means 7 for inserting a transmitting a channel from the CPU or through the external line into the transmission data stream. D channel separating / inserting means (10) which connects to the D channel from the received data, or inserts into the transmitting data stream for the transmitting D channel coming from the CPU, and externally enters the buffer buffer memory means (5). Connected to the line, extract the frame pattern from the received data and find out the exact frame position by comparing with the generated frame, compare it for 4 frame periods, and output the frame synchronous signal when it is continuously matched. Receiving frame synchronizing means 11 for outputting, timing signal generating means 12 for generating necessary timing signals in the apparatus, and Digital phase locked loop means 13 receiving frame clock from timing signal generating means 12 and generating system clocks F0, C4 and C2, receiving frame signal from timing generating means 12, and transmitting. Generation of a transmission frame clock which receives a transmission frame insertion means 14 and an internal clock C400x for generating a frame signal and inserting the frame signal into an external line of the buffer buffer memory means 5 and generating a transmission frame signal FRBx. The means 15 receives the reference frame clock RER, receives the transmission clock generating means 16 for generating the internal system clocks C400x and C800x, the receiving frame clock FRBr and the internal clock C400r. A channel timing signal generating means 18 receiving a channel timing signal generating means 7 for generating a channel timing signal and a clock required for the speed converting means 7 by receiving system clocks F0 and C2. Consisting of Common Channel Control Device. 2. The common channel control apparatus according to claim 1, wherein the B channel timeslot assignment means (8) is configured to condense 8B channel information coming from the line into a 5B channel or to allocate 5B channel information to an 8B channel. 2. The common channel control apparatus according to claim 1, wherein the channel rate converting means converts a 400kbps data rate into a 2.048kbps rate or converts a 2.048kbps data rate into a 400kbps rate.

Images