KR910001775A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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Publication number
KR910001775A
KR910001775A KR1019900009538A KR900009538A KR910001775A KR 910001775 A KR910001775 A KR 910001775A KR 1019900009538 A KR1019900009538 A KR 1019900009538A KR 900009538 A KR900009538 A KR 900009538A KR 910001775 A KR910001775 A KR 910001775A
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KR
South Korea
Prior art keywords
transistor
hot wire
gate
threshold voltage
potential
Prior art date
Application number
KR1019900009538A
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Korean (ko)
Other versions
KR930008413B1 (en
Inventor
히로시 이와하시
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR910001775A publication Critical patent/KR910001775A/en
Application granted granted Critical
Publication of KR930008413B1 publication Critical patent/KR930008413B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Abstract

내용 없음No content

Description

반도체 기억장치Semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예를 적용시킨 반도체기억장치의 전체 회로도.1 is an overall circuit diagram of a semiconductor memory device to which the first embodiment of the present invention is applied.

제2도는 본 발명의 제2실시예의 회로도.2 is a circuit diagram of a second embodiment of the present invention.

Claims (4)

행선(11~1n)과, 이 행선에 의해 선택적으로 구동되는 메모리셀(311~3nm), 이 메모리셀에 접속되는 열선(21~2m), 이 열선에 (21~2m), 이 이 열선에 접속되는 부하트랜지스터(16), 이 부하트랜지스터와 상기 열선의 사이에 소오스/드레인전류로가 접속되어 상기 열선의 전위에 따라 게이트전위가 제어되는 제1트랜지스터(15.15A), 상기 열선에 접속되어 상기 열선의 전위가 소정의 전위 이상일때 상기 열선의 전위를 상기 소정의 전위까지 방전시키는 방전수단(21~26.I)를 구비한 것을 특징으로 하는 반도체 기억장치.Routing (1 1 ~ 1n) and, optionally a memory cell (3 11 ~ 3nm), hot wire which is connected to the memory cells (2 1 ~ 2m), ( 2 1 ~ 2m) in the heating coil is driven by a routing, A load transistor 16 connected to the hot wire, a first transistor 15.15A having a source / drain current path connected between the load transistor and the hot wire to control a gate potential according to the potential of the hot wire, and the hot wire And discharging means (21 to 26.I) connected to to discharge the electric potential of the hot wire to the predetermined electric potential when the electric potential of the hot wire is equal to or higher than the predetermined electric potential. 제1항에 있어서, 상기 소정의 전위는 상기 제1트랜지스터의 게이트전위 보다도 제1트랜지스터의 문턱치 전압 분만큼 낮은 값인 것을 특징으로 하는 반도체 기억장치.The semiconductor memory device according to claim 1, wherein the predetermined potential is lower than the gate potential of the first transistor by the threshold voltage of the first transistor. 제1항에 있어서, 상기 방전수단은 상기 열선에 드레인과 게이트가 접속된 문턱치 전압이 대략 0V인 제2트랜지스터(23)를 구비하고, 그 제2트랜지스터의 소오스를 전원단자에 접지사이에 직렬로 접속된 제3트랜지스터(21) 및 제4트랜지스터(24)의 접속중점에 접속시키며 상기 제3트랜지스터(21)의 게이트를 상기 제1트랜지스터(15)의 게이트에 접속시킨 구성으로 되어 있고, 더욱이 상기 제1트랜지스터의 문턱치 전압과 제3트랜지스터의 문턱치 전압이 거의 동일한 것을 특징으로 하는 반도체 기억장치.2. The discharge device according to claim 1, wherein the discharging means includes a second transistor (23) having a threshold voltage of approximately 0 V connected to a drain and a gate connected to the hot wire, and the source of the second transistor is connected in series between the ground and the power supply terminal. The gate of the third transistor 21 is connected to the gate of the first transistor 15 while the third transistor 21 and the fourth transistor 24 are connected to each other. And the threshold voltage of the first transistor is substantially equal to the threshold voltage of the third transistor. VV 제1항에 있어서, 상기 제1트랜지스터는 문턱치 전압이 대략0V인 트랜지스터이고, 상기 방전수단은 상기 열선과 상기 제1트랜지스터의 게이트 사이에 접속된 문턱치 전압이 대략 0V인 제5트랜지스터(26)를 구비하여 그 제5트랜지스터(26)의 게이트를 상기 열선에 접속시킨 것임을 특징으로 하는 반도체기억장치.2. The first transistor of claim 1, wherein the first transistor is a transistor having a threshold voltage of approximately 0 V, and the discharging means includes a fifth transistor 26 having a threshold voltage of approximately 0 V connected between the heating wire and the gate of the first transistor. And a gate of the fifth transistor (26) connected to the hot wire. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900009538A 1989-06-27 1990-06-27 Semicondcutor memory device KR930008413B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16497089A JPH0814996B2 (en) 1989-06-27 1989-06-27 Semiconductor memory device
JP1-164970 1989-06-27
JP89-164970 1989-06-27

Publications (2)

Publication Number Publication Date
KR910001775A true KR910001775A (en) 1991-01-31
KR930008413B1 KR930008413B1 (en) 1993-08-31

Family

ID=15803341

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900009538A KR930008413B1 (en) 1989-06-27 1990-06-27 Semicondcutor memory device

Country Status (3)

Country Link
US (1) US5175705A (en)
JP (1) JPH0814996B2 (en)
KR (1) KR930008413B1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0478097A (en) * 1990-07-13 1992-03-12 Sony Corp Memory device
JP3404127B2 (en) * 1994-06-17 2003-05-06 富士通株式会社 Semiconductor storage device
US5675539A (en) * 1994-12-21 1997-10-07 Sgs-Thomson Microelectronics, S.A. Method and circuit for testing memories in integrated circuit form
DE69520495T2 (en) * 1995-08-04 2001-07-12 St Microelectronics Srl Read circuit for non-volatile memories
US6487123B1 (en) * 1999-10-04 2002-11-26 Seiko Epson Corp Semiconductor integrated circuit, ink cartridge having the semiconductor integrated circuit, and inkjet recording device having the ink cartridge attached
FR2853444B1 (en) * 2003-04-02 2005-07-15 St Microelectronics Sa READING DUAL-READING READING AMPLIFIER
US7813157B2 (en) * 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2070372B (en) * 1980-01-31 1983-09-28 Tokyo Shibaura Electric Co Semiconductor memory device
US4542485A (en) * 1981-01-14 1985-09-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit
JPS58185094A (en) * 1982-04-24 1983-10-28 Toshiba Corp Semiconductor integrated circuit
JPS5977700A (en) * 1982-10-25 1984-05-04 Toshiba Corp Non-volatile semiconductor memory device
JPS60136996A (en) * 1983-12-26 1985-07-20 Toshiba Corp Semiconductor storage device
US4694429A (en) * 1984-11-29 1987-09-15 Kabushiki Kaisha Toshiba Semiconductor memory device
US4769784A (en) * 1986-08-19 1988-09-06 Advanced Micro Devices, Inc. Capacitor-plate bias generator for CMOS DRAM memories
US4797856A (en) * 1987-04-16 1989-01-10 Intel Corporation Self-limiting erase scheme for EEPROM
JP2583606B2 (en) * 1989-05-16 1997-02-19 富士通株式会社 Sense amplifier circuit

Also Published As

Publication number Publication date
JPH0330192A (en) 1991-02-08
US5175705A (en) 1992-12-29
JPH0814996B2 (en) 1996-02-14
KR930008413B1 (en) 1993-08-31

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