JPS5977700A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To supply stable source potential with no influence affected by the variation of a process with simple constitution by forming a common source potential setting circuit for a non-volatile memory cell array by a diode and a switching MOS transistor (TR). CONSTITUTION:The common source potential setting circuit for the non-volatile memory cell array 10 is formed by p-n junction diode 21 and a MOS switching TR22 connected to the diode 21 in parallel, and at the reading mode, the TR22 is on and the common source potential is set up to almost the earth potential. At the writing mode, the TR22 is turned off and the built-in potential of the diode 21 is turned to the setting potential of the common source, a fixed potential with high controlling property based upon the characteristics of the diode 21, so that a non-selective cell is prevented from current leakage. Consequently, the stable source potential can be supplied with no influence affected by the variation of the process with the simple constitution.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to non-volatile semiconductor memory devices.

In particular, the present invention relates to improvements in common source OJ potential setting circuits for memory cell arrays.

[Technical background of the invention and its problems]

In a non-volatile memory such as SAM (J8), a source potential setting circuit is generally provided at the common source of the memory cell array, and the common source potential is set to about 1ν at the time of filling.
It prevents leakage current in non-selected cells and increases the embedding speed.

FIG. 1 shows a conventional example of a common source low level setting circuit OJ for a memory cell array based on an N-channel l/D type M (J8 circuit ζ: memory cell array 1o is, for example, an N-channel M
A M (J8, the source potential setting circuit is E type N
Channel M (J8) transistor 11, '12.13.1
4.16.18 and L) type N-channel 08 transistor 15.17 ◎ In read mode, clock φ is at high level, transistor 12 is off, transistor 14 is on, and memory cell array 10 ( b To the common source node 1 is kept at approximately the ground potential @ In the write mode, the clock φ is set to high level, transistor 12 is turned on, and transistor j4jl is turned off [At this time, to the common source node.

But transistor 15 y2 load, ) range meta 131:! : Threshold value of the inverter circuit used as a driver - Ratio or higher
to the node, is at high level t: rl, transistor 18
tries to return the node N, to the low level C2 ◎ Reverse ≦ to the nine-node, and when the upper half of the inverter tries to go below the threshold voltage of the inverter, it tries to return the node N, to the low level C2 according to the same principle. □The threshold voltage of the upper 6 inverter circuits is almost equal to the threshold voltage of the transistor 13, so if the threshold voltage of the transistor 13 &lV is kept close to the common source node, then IVI/J However, this conventional circuit example has the disadvantage that if the threshold voltage of the transistor 13 varies, the potential of the node N will also vary, causing the writing characteristics to vary.
[Object of the Invention] The present invention was made in view of the above-mentioned circumstances.

Its purpose is to supply a stable source potential unaffected by process variations to the common first-generation sources 62 of the memory cell array. An object of the present invention is to provide a non-volatile semiconductor memory device provided with a source level setting circuit having a simple configuration. Generates a common source potential for the cell array. In read mode C2,
Switching MO8 connected in parallel with junction diode to P
) By turning on the transistor T, the common source potential is kept at approximately ground level 4.

〔Effect of the invention〕

PN junction diode-F CI) Built-in potential is MtJ8
Compared to the threshold voltage of a transistor, there are fewer variations in the manufacturing process and it is stable. Therefore, according to the present invention C, the common source potential at the time of writing to the memory cell array is set stably to make the writing characteristics uniform. The configuration of the source potential setting circuit is extremely simple.
[Embodiments of the Invention] The present invention will be described in detail below with reference to IQtThv. FIG. 2 shows the circuit configuration of one embodiment of memory cell array 1.
0 is the same as in Figure 1 1 For example, N channel 8AMtJ
8i was used. A common source node N of this memory cell array 10.

The source potential setting circuit provided in
J8) transistor 22.

This (IJ i' N-junction diode 21 is a p-type at substrate 31 CN as shown in FIG.
After forming the type well 32, a field oxide film 33t' is formed.
After that, a P-type layer 34 is formed by ion implantation and resist. Use a mask to selectively implant ions into the N+ type layer 35. When the memory of the OJ embodiment is in continuous mode, a junction diode is formed to I and P by contacting () and (respectively).

When the clock voltage is at a high level, the Mυ8 transistor 22 is turned on, and the node N1 becomes approximately at the ground level. In write mode, clock 1 is low level and ML+8
) The transistor 22 is turned off and the node N becomes a junction diode to P.

21 building) In potential (approximately 0.55 V) C:f(
According to this embodiment, the common source potential of the memory cell array is constant at the time of charging t:P N diode characteristic C; In addition, the source potential setting circuit has a much slower structure than the conventional one.In the above embodiment, one P
Although an N-junction diode was used, two PN-junction diodes may be connected in series as shown in the fourth factor.
This reduces the common source potential to approximately 0.65 x2 V =
1.3 V 1m can be set0Also, in the above embodiment, the case where the peripheral circuit is a Hellael type CM (Jfli structure) is explained, but the present invention is a P-well type CM08g.
Similarly, twin-well type C1vIUS≠structure, or epitaxial CM (when using J8 structure tube-side circuit C2, or when using intermediate C2 rewritable memory cell!) are also applicable. can do.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conventional circuit, Fig. 2 is a diagram showing an OJ circuit of an embodiment of the present invention, Fig. 3 is a diagram showing the structure of a PN junction diode of the same embodiment, and Fig. 4 is a diagram of the present invention. Other embodiments of
It is a figure which shows melting of a PN diode part. DESCRIPTION OF SYMBOLS 10...Memory cell array, Nl...Common source node, 21...PN junction diode, 22...Switching M (J8) transistor, 31...P recovery substrate, 32...N type well , 33...Field oxide film, 34...P type layer, 35...N type layer P applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) In a non-volatile semiconductor memory device, a source potential setting circuit is provided around a memory cell array in which non-volatile semiconductor memory elements are arranged, for setting a common source of this memory cell array to different potentials during writing and when writing successively. , the source potential setting circuit includes a P-junction diode connected between the common source and the ground terminal, and a switching M (J8) junction diode connected in parallel to this diode and controlled on/off according to the operation mode of the memory. A non-volatile semiconductor memory device characterized by comprising: (2) The peripheral circuit of the memory cell array is CM (J8
It's a circuit, lr? The nonvolatile semiconductor memory device according to claim 1, wherein the PN junction diode is formed in a second m-type well formed in a first s-type substrate.