CN112185965B - Mask read-only memory - Google Patents
Mask read-only memory Download PDFInfo
- Publication number
- CN112185965B CN112185965B CN202011261858.5A CN202011261858A CN112185965B CN 112185965 B CN112185965 B CN 112185965B CN 202011261858 A CN202011261858 A CN 202011261858A CN 112185965 B CN112185965 B CN 112185965B
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- gate
- grid electrode
- electrode
- mask rom
- mask
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- 239000000758 substrate Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
- G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
Abstract
The invention discloses a mask read-only memory, which comprises: the grid electrode region comprises a grid electrode formed by a plurality of transistors connected in series and is used for storing information and controlling information read-out of the mask read-only memory under the control of grid electrode voltage, and each transistor shares a source electrode and a drain electrode; a drain electrode region for forming a drain electrode of the mask ROM; the source electrode area is used for forming the source electrode of the mask read-only memory and saving the layout area.
Description
Technical Field
The invention relates to the field of memory design, in particular to a Mask ROM (Mask Read Only Memory, mask ROM, mask read only memory).
Background
Currently, the memory of a microprocessor MCU can be divided into 3 types: MASK ROM, OTP ROM, FLASH ROM. The MCU program of the FALSH ROM can be repeatedly erased and written, has strong flexibility and higher price, and is suitable for application occasions insensitive to price or development purposes; the MCU price of the OTP ROM is between the two, and the OTP ROM has one-time programmable capability, so that the OTP ROM is suitable for application occasions which not only require certain flexibility but also require low cost, and particularly electronic products with continuously updated functions and rapid mass production; the MCU of the MASK ROM has low price, but the program is solidified when leaving the factory, can not be modified after production, has low cost when mass production, and is very suitable for application occasions with the fixed program, such as reversing a voice chip or backing up the original program of the system.
The conventional Mask ROM (Mask Read Only Memory, mask ROM) is essentially a transistor (transistor) which is turned on or off according to the threshold voltage, so that reading of 1 or 0 is realized, but each transistor in the prior art requires a separate source and drain, so that each memory cell (cell) occupies a large area.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a mask ROM that saves the occupied area.
To achieve the above object, the present invention provides a mask ROM comprising
The grid electrode region comprises a grid electrode formed by a plurality of transistors connected in series and is used for storing information and controlling information read-out of the mask read-only memory under the control of grid electrode voltage, and each transistor shares a source electrode and a drain electrode;
a drain electrode region for forming a drain electrode of the mask ROM;
and the source electrode region is used for forming a source electrode of the mask read-only memory.
Preferably, for the selected transistor, its gate is connected to the 1/2 power supply voltage vdd, and the gate of the unselected transistor is connected to the power supply voltage vdd.
Preferably, the gate region includes at least a first gate and a second gate, the first gate and the second gate sharing the source and the drain.
Preferably, when reading the information stored in the first gate, the bias voltage of the second gate is connected to the power voltage vdd, the bias voltage of the first gate is connected to the 1/2 power voltage vdd, and the source is connected to 0V at this time, and the reading is performed on the bit line BL.
Preferably, the threshold value of the transistor with the first gate as the gate electrode determines whether the channel of the mask ROM is turned on or off.
Preferably, when reading the information stored in the second gate, the bias voltage of the first gate is connected to the power supply voltage vdd, the bias voltage of the second gate is connected to the 1/2 power supply voltage vdd, and the source is connected to 0V at this time, and the reading is performed on the bit line BL.
Preferably, the threshold value of the transistor with the second gate as the gate electrode determines whether the channel of the mask ROM is turned on or off.
Preferably, for two transistors having a first gate and a second gate as gates, two threshold voltages Vth1, vth2 are achieved by ion implantation.
Preferably, the drain region is formed by heavily doping the P-type substrate with an N-type.
Preferably, the source region is formed by heavily doping the P-type substrate with an N-type.
Compared with the prior art, the mask read-only memory has the advantages that the plurality of transistors (transistors) sharing the drain electrode and the source electrode are connected in series to serve as the grid electrode of the mask read-only memory, the grid electrode of the selected transistor is connected with 1/2vdd, and the grid electrode of the unselected transistor is connected with the power supply voltage vdd, so that the mask read-only memory capable of saving the occupied area of a chip is realized.
Drawings
FIG. 1 is a schematic diagram of a mask ROM according to the present invention;
FIG. 2 is a schematic diagram of a novel mask ROM application according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following disclosure, when considered in light of the accompanying drawings, by describing embodiments of the present invention with specific embodiments thereof. The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
Fig. 1 is a schematic diagram of a mask rom according to the present invention. As shown in fig. 1, a Mask read only memory (Mask ROM) of the present invention includes a gate region 10, a drain region 20, and a source region 30.
Wherein the gate region 10 is composed of a first gate (G1) 101 and a second gate (G2) 102 for storing information and controlling information readout of the Mask read-only memory (Mask Read Only Memory, mask ROM) of the present invention under control of gate voltage; a drain region 20, formed of an N-type heavily doped (n+) on the P-type substrate, for forming the drain of the Mask ROM (Mask Read Only Memory, mask ROM) of the present invention; the source region 30, which is formed by heavily doping n+ on a P-type substrate, is used to form the source of the Mask ROM (Mask Read Only Memory, mask ROM) of the present invention.
Essentially, the novel mask ROM of the present invention is a transistor (transistor) having a first gate G1 and a second gate G2 as gates, and the two transistors share a source S and a drain D.
For two transistors (transistors) having the first gate G1 and the second gate G2 as gates, two threshold voltages Vth1, vth2, respectively 1/3vdd, 2/3vdd, can be realized by ion implantation (implant).
Fig. 2 is a schematic diagram of a novel mask rom application of the present invention, where a first gate G1 is connected to a first bias voltage Vbias1, a second gate G2 is connected to a second bias voltage Vbias2, a source S is connected to 0V (ground), and a drain D is connected to a bit line BL.
When reading information stored in the first gate G1, the bias voltage Vbias2 of the second gate G2 is connected to the power supply voltage vdd, no matter whether the transistor corresponding to the second gate G2 is a low threshold or a high threshold, the transistor taking the second gate G2 as the gate is in an on state, the bias voltage Vbias1 of the first gate G1 is connected to 1/2vdd, the threshold of the transistor taking the first gate G1 as the gate determines that the channel of the whole Mask read-only memory (Mask Read Only Memory, mask ROM) is turned on or off, at this time, S is connected to 0V (ground), and reading is performed on the bit line BL.
When reading information stored in the second gate G2, the bias voltage Vbias1 of the first gate G1 is connected to the power supply voltage vdd, the transistor taking the first gate G1 as the gate is in an on state no matter whether the transistor corresponding to the first gate G1 is a low threshold or a high threshold, the bias voltage Vbias2 of the second gate G2 is connected to 1/2vdd, the threshold of the transistor taking the second gate G2 as the gate determines that the channel of the whole Mask read-only memory (Mask Read Only Memory, mask ROM) is turned on or turned off, at this time, S is connected to 0V (ground), and reading is performed on the bit line BL.
In an expandable manner, three or more transistors (transistors) sharing a drain and a source may be connected in series, wherein the transistors sharing the source and the drain have three or more gates G1, G2, … …, gn, and the threshold value corresponding to the gates may be 1/3vdd or 2/3vdd, the gate of the selected transistor is connected to 1/2vdd, and the gate of the unselected transistor is connected to the power supply voltage vdd.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be indicated by the appended claims.
Claims (9)
1. A mask ROM comprises
The grid electrode region comprises a grid electrode formed by a plurality of transistors connected in series and is used for storing information and controlling information reading of the mask read-only memory under the control of grid voltage, and each transistor shares a source electrode and a drain electrode, wherein the grid electrode region at least comprises a first grid electrode and a second grid electrode, and the first grid electrode and the second grid electrode share the source electrode and the drain electrode;
a drain electrode region for forming a drain electrode of the mask ROM;
and the source electrode region is used for forming a source electrode of the mask read-only memory.
2. A mask rom as defined in claim 1, wherein: for the selected transistor, the gate is connected with 1/2 power supply voltage vdd, and the gate of the unselected transistor is connected with power supply voltage vdd.
3. A mask rom as defined in claim 1, wherein: when the information stored in the first grid electrode is read, the bias voltage of the second grid electrode is connected with the power supply voltage vdd, the bias voltage of the first grid electrode is connected with the 1/2 power supply voltage vdd, and at the moment, the source electrode is connected with 0V, and reading is performed on the bit line BL.
4. A mask rom as claimed in claim 3, wherein: and determining that the channel of the mask read-only memory is conducted or closed according to the threshold value of the transistor taking the first grid electrode as the grid electrode.
5. A mask rom as defined in claim 1, wherein: when the information stored in the second gate is read, the bias voltage of the first gate is connected to the power supply voltage vdd, the bias voltage of the second gate is connected to the 1/2 power supply voltage vdd, and at this time, the source is connected to 0V, and the information is read on the bit line BL.
6. A mask rom as defined in claim 5, wherein: and determining that the channel of the mask read-only memory is on or off according to the threshold value of the transistor taking the second grid electrode as the grid electrode.
7. A mask rom as claimed in claim 4 or 6, wherein: for two transistors having a first gate and a second gate as gates, two threshold voltages Vth1, vth2 are realized by ion implantation.
8. A mask rom as defined in claim 1, wherein: the drain region is formed by heavily doping an N type on a P type substrate.
9. A mask rom as defined in claim 1, wherein: the source electrode region is formed by heavily doping an N type on a P type substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011261858.5A CN112185965B (en) | 2020-11-12 | 2020-11-12 | Mask read-only memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011261858.5A CN112185965B (en) | 2020-11-12 | 2020-11-12 | Mask read-only memory |
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| Publication Number | Publication Date |
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| CN112185965A CN112185965A (en) | 2021-01-05 |
| CN112185965B true CN112185965B (en) | 2023-11-10 |
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| CN202011261858.5A Active CN112185965B (en) | 2020-11-12 | 2020-11-12 | Mask read-only memory |
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Citations (14)
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| US6417548B1 (en) * | 1999-07-19 | 2002-07-09 | United Microelectronics Corp. | Variable work function transistor high density mask ROM |
| CN1702875A (en) * | 2004-05-25 | 2005-11-30 | 海力士半导体有限公司 | Transistor and method for manufacturing the same |
| CN1841782A (en) * | 2005-01-03 | 2006-10-04 | 旺宏电子股份有限公司 | Non-volatile memory cells, memory arrays including the same and methods of operating memory cells and arrays |
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| CN104617097A (en) * | 2013-11-05 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Mask read only memory and manufacturing method thereof |
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Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030232284A1 (en) * | 2002-06-12 | 2003-12-18 | Chien-Hung Liu | Method of forming a system on chip |
| US6856533B2 (en) * | 2003-04-17 | 2005-02-15 | Macronix International Co., Ltd. | Method of modulating threshold voltage of a mask ROM |
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2020
- 2020-11-12 CN CN202011261858.5A patent/CN112185965B/en active Active
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| US5891779A (en) * | 1997-11-28 | 1999-04-06 | United Microelectronics Corp. | Method of fabricating tetra-state mask read only memory |
| US6417548B1 (en) * | 1999-07-19 | 2002-07-09 | United Microelectronics Corp. | Variable work function transistor high density mask ROM |
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| CN112185965A (en) | 2021-01-05 |
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