KR910001472Y1 - Picture memory clock generation circuit - Google Patents

Picture memory clock generation circuit Download PDF

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Publication number
KR910001472Y1
KR910001472Y1 KR2019860007595U KR860007595U KR910001472Y1 KR 910001472 Y1 KR910001472 Y1 KR 910001472Y1 KR 2019860007595 U KR2019860007595 U KR 2019860007595U KR 860007595 U KR860007595 U KR 860007595U KR 910001472 Y1 KR910001472 Y1 KR 910001472Y1
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unit
signal
phase
output signal
clock
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KR2019860007595U
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KR870019326U (en
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김기범
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삼성전자 주식회사
한형수
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/95—Time-base error compensation
    • H04N5/956—Time-base error compensation by using a digital memory with independent write-in and read-out clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/44—Colour synchronisation
    • H04N9/455—Generation of colour burst signals; Insertion of colour burst signals in colour picture signals or separation of colour burst signals from colour picture signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음.No content.

Description

영상 메모리용 클럭 발생회로Clock Generation Circuit for Image Memory

제1도는 본 고안의 블럭도.1 is a block diagram of the present invention.

제2도는 본 고안의 상세한 회로도.2 is a detailed circuit diagram of the present invention.

제3도는 제2도의 각 부분에서의 파형도.3 is a waveform diagram at each part of FIG. 2;

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 변환부 2 : 1차 분주부1: converting unit 2: primary dispensing unit

3 : 여파부 4 : 위상동기제어부3: filter part 4: phase synchronization control part

5 : 2차 분주부 C1-C10: 콘덴서5: secondary dispensing part C 1 -C 10 : condenser

R1-R11: 저항 G1-G4: 반전게이트R 1 -R 11 : Resistor G 1 -G 4 : Inverting gate

Q1, Q2: 트랜지스터 L : 코일Q 1 , Q 2 : Transistor L: Coil

CTR1, CTR2: 카운터 PLL : 위상동기계CTR 1 , CTR 2 : Counter PLL: Phase Dynamic Machine

본 고안은 아날로그(Analog)인 영상신호를 메모리(Memory)에 기억시키기 위하여 디지탈(digital)신호로 변환하는 클럭(C1ock)발생회로에 관한 것이다.The present invention relates to a clock generator circuit for converting an analog image signal into a digital signal for storing in an memory.

종래에는 자유발진 크리스탈(Crystal)발진기를 사용하여 출력되는 클럭을 이용할 때, 영상신호중의 칼라 버스트(Color Burst) 신호와 클럭간에 발진 주파수를 제어하는 로킹(Locking) 이 안되고, 클럭이 자유발진을 하기때문에 영상신호를 메모리에 기억시켰다가 재생할 때의 색상에 있어서 오차가 발생하여 화상의 선명도가 떨어지는 문제점이 있었다.Conventionally, when using a clock output using a free oscillating crystal oscillator, there is no locking to control the oscillation frequency between a color burst signal and a clock in an image signal, and the clock is free oscillating. As a result, an error occurs in color when the video signal is stored in the memory and reproduced, resulting in a decrease in image clarity.

따라서 본 고안의 목적은 상기한 문제점을 해결하기 위해 안출한 것으로서 자유발진 크리스탈 발진기를 사용하지 않고 집적회로를 사용하여 칼라 버스트 신호와 로킹되는 클럭을 발생하는 회로를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a circuit for generating a color burst signal and a clock that is locked by using an integrated circuit without using a free oscillating crystal oscillator.

이하 첨부된 도면을 참조하여 본 고안의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 고안의 블럭도로서, 변환부(1)는 수신되는 비데오 신호중 칼라 버스트를 정형화시켜서 집적회로에 인가하는 신호로 변환시키는 회로이고, 1차 분주부(2)는 변환부{1)의 출력신호를 4로 분주하는 회로이며, 여파부(3)는 분주된 신호를 인가하여 고주파만을 통과시켜 출력하는 회로이다.FIG. 1 is a block diagram of the present invention, wherein the conversion unit 1 is a circuit for converting a color burst of a received video signal into a signal applied to an integrated circuit, and the primary division unit 2 is a conversion unit {1]. Is a circuit for dividing the output signal into 4, and the filter unit 3 is a circuit for applying the divided signal and passing only the high frequency.

그리고 위상동기 제어부(4)는 입력신호의 위상을 제어하여 일정 클럭신호를 출력하는 회로이고, 2차 분주부 (5)는 위상동기 제어부(4)의 출력신호를 인가하여 16으로 분주하여 위상동기 제어부(4)에 피이드 백(Feed Back))되도록 인가하는 회로이다.The phase synchronous controller 4 is a circuit for controlling the phase of the input signal and outputting a predetermined clock signal, and the secondary frequency divider 5 divides the output signal of the phase synchronous controller 4 into 16 to divide the phase synchronously. The circuit is applied to the control unit 4 so as to feed back.

상기한 구성을 갖는 본 고안의 상세한 회로도는 제2도에 도시되어 있다.A detailed circuit diagram of the present invention having the above configuration is shown in FIG.

수신되는 영상신호중 칼라 버스트를 검출하여서 본 고안의 변환부(1)에 인가하여 정형 및 집적회로에 인가하되는 신호로 변환되는데, 이 칼라 버스트 신호가 콘덴서(C1)와 저항(R1)을 거쳐 트랜지스터(Q1)이 베이스에 인가되고, 전원(Vcc)이 트랜지스터(Q1)의 콜렉터에 인가되어서 에미터와 저항(R2)을 거쳐 접지 또는 트랜지스터(Q2)의에 인가되며, 트랜지스터(Q1)의 에미터에 나타난 신호는 콘덴서(C2)를 거쳐 트랜지스티(Q2)의 베이스에 인가되고 또한 콘덴서(C2)와 저항(R3)을 거쳐 트랜지스터(Q2)의 콜렉터에 인가된다.The color burst of the received video signal is detected and applied to the converter 1 of the present invention and converted into a signal applied to the shaping and integrated circuit. The color burst signal is used to convert the capacitor C 1 and the resistor R 1 . Transistor Q 1 is applied to the base via power supply Vcc to the collector of transistor Q 1 and is applied to the ground or to transistor Q 2 via the emitter and resistor R 2 . applied to the base of (Q 1) Transitional stitcher (Q 2) signals shown in the emitter is through a capacitor (C 2) of and addition of the capacitor (C 2) and a resistance the transistor (Q 2) (R 3) through the Applied to the collector.

그리고 트랜시스터(Q2)의 콜렉터에는 직렬연결된 코일(L)과 저항(R4)을 거쳐 전원이 인가되고, 이 트랜지스터(Q2)의 콜렉터에 나타난 신호는 직렬연결된 반전게이트(G1, G2)를 거쳐 방형되어서 카운터(CTR1)에 인가되어 4로 분주된다.And transfected sister (Q 2) collector has been powered through the series-connected coil (L) and a resistance (R 4) is applied, the signal shown in the collector of the transistor (Q 2) is connected in series inverting gate (G 1, G It is square through 2 ) and is applied to the counter CTR 1 and divided into four.

상기한 카운터(CTR1)에서 분주되어 출력된 신호는 병렬연결된 저항(R5)과 콘덴서(C3) 및 접지된 저항(R6)을 거쳐 위상동기계(PLL)의 입력단(IN2)에 인가하고, 위상을 제어하기 위하여 병렬연결된 가변저항(R6)과 콘덴서(C1)를 거쳐 위상동기계(PLL)의 입력단(P1)에 인가하며, 접지된 콘덴서(C6-C8)는 병렬로하여 위상동기계(PLL)의 입력단(P2-P4)에 인가한다.The signal divided and output from the counter (CTR 1 ) is output to the input terminal (IN 2 ) of the phase shifting machine (PLL) through a parallel connected resistor (R 5 ), a capacitor (C 3 ), and a grounded resistor (R 6 ). In order to control the phase, it is applied to the input terminal (P 1 ) of the phase shifting machine (PLL) via a parallel resistor (R 6 ) and a capacitor (C 1 ) connected in parallel, and the grounded capacitor (C 6 -C 8 ) Are applied in parallel to the input terminals P 2 -P 4 of the phase-locking machine PLL.

그리고 병렬연결된 콘덴서(C9,C10)의 양단에는 위상동기계(PLL)의 인가단자(P6, P7)가 연결되고, 위상 제어된 출력신호는 위상동기계(PLL)의 출력단(OUT)을 통하여 저항(R9)가 전원이 양분되는 저항(R16, R11)사이의 일단과 직렬연결된 반전게이트(G3, G4)를 거쳐서 출력된다.Application terminals P 6 and P 7 of the phase-locked machine PLL are connected to both ends of the parallel-connected capacitors C 9 and C 10 , and the phase-controlled output signal is output to OUT of the phase-locked machine PLL. The resistor R 9 is output through the inverting gates G 3 and G 4 connected in series with one end between the resistors R 16 and R 11 through which power is divided.

이때의 출력신호(Mout)는 카운터(CTR2)의 입력단(IN)에 인가되어 출력단(OUT)에는 16으로 분주된 신호가 출력되어서 위상동기계(PLL)의 입력단(IN1)에 피이드 백 된다.At this time, the output signal Mout is applied to the input terminal IN of the counter CTR 2 , and a signal divided by 16 is output to the output terminal OUT and fed back to the input terminal IN 1 of the phase-locked machine PLL. .

이와같은 구성을 갖는 본 고안의 영상 메모리용 클럭 발생회로에 있어서 인가되는 칼라 버스트신호를 이용하여 영상 메모리에 저장되는 클럭신호가 발생되는 회로동작을 설명하면 다음과 같다.The circuit operation of generating a clock signal stored in the image memory using the color burst signal applied in the clock memory circuit for the image memory having the above structure will be described below.

수신기에서 수신되는 영상신호중 칼라비스트를 검출하여서 번환부(1)의 콘덴서(C1)와 저항(R1)을 통해 트랜지스터(Q1) 의 베이스에 인가되면, 트랜지스터(Q2) 의 콜렉터에는 제3도(a)와 같은 구형파(3,579545MHZ) 가 발생되어 반전게이트(G1,G2)를 연속해서 통과하면 정형된다.When the color bias is detected in the image signal received from the receiver and applied to the base of the transistor Q 1 through the capacitor C 1 and the resistor R 1 of the switching unit 1, the collector of the transistor Q 2 is supplied to the collector. A square wave 3,579545MH Z as shown in FIG. 3 (a) is generated, and is successively passed through the inverting gates G 1 and G 2 .

이 정형된 신호는 카운터(CTR1)에 의해서 4로 분주되어 출력된 신호를 고역 필터링(Filtering)하면, 고주파수만 통과되어 위상동기계(PLL)이 입력단(IN2)에 인가된 신호(제3도의 "B")는 가변저항(R6)과 콘뎬서(C5, C9, C10)에 의해서 입력신호를 위상제어하고 출력한다.The shaped signal is divided into four by the counter CTR 1 and when the high frequency filtering signal is outputted, only the high frequency passes and the phase shifting device PLL is applied to the input terminal IN 2 (third). degree "B") is the phase control, and outputs the input signal by the variable resistor (R 6) and cone dyenseo (C 5, C 9, C 10).

이때 위상동기계(PLL)의 출력단(OUT)에는 제3도(C)와 같은 클럭(14,31818MHZ)이 발생되어서 정형된 후, 다시 카운터(CTR2)에서 제3도의 "D"와 같이 16으로 분주한 다음 위상동기계(PLL)의 입력단(IN1)에 피이드백 시킨다.At this time, the clock 14,31818MH Z as shown in FIG. 3C is generated at the output terminal OUT of the PLL, and then the counter CTR 2 is again shown as "D" in FIG. Dispense it to 16 and feed it back to the input terminal IN 1 of the PLL.

따라서 위상동기계(PLL)에 입력된 위상차가 있는 두신호를 위상비교하여서 14,31818MHZ의 주파수를 갖는신호(제3도의 "E")가 출력되게 한다.Therefore, by comparing the two signals with the phase difference input to the phase dynamic machine (PLL), a signal having a frequency of 14,31818MH Z ("E" in FIG. 3) is output.

이상과 같이 본 고안에 의하면 영상 메모리에 저장되는 클럭이 재생시에는 색상의 완전한 복조가 이루어져서 에러발생이 없고, 이에 따른 화상의 선명도를 향상시킬 수 있다.As described above, according to the present invention, when the clock stored in the image memory is reproduced, color demodulation is performed, so that no error occurs, thereby improving the sharpness of the image.

Claims (1)

수신되는 비데오 신호중 칼라 버스트를 정형화시켜서 구형파로 변환시키는 변환부(1)와, 상기한 변환부(1)의 출력신호를 4로 분주하는 1차 분주부(2)와, 상기한 1차 분주부(2)의 출력신호를 고역 필터링하여 고주파만을 출력하는 여파부(3)와, 상기한 여파부(3)의 출력신호와 2차 분주부(5)를 통하여 피이드 백된 신호를 위상비교하여 14,318l8MHz 의 주파수를 갖는 클럭을 발생시키는 위상동기 제어부(4)와, 상기한 위상동기 제어부(4)의 출력신호를 16으로 분주하여 위상동기 제어부(4)에 다시 피이드 백 시키는2차 분주부(5)로 이루어진 것을 특징으로 하는 영상 메모리용 클럭 발생회로.A conversion unit 1 for shaping the color burst among the received video signals and converting the color burst into a square wave, a primary division unit 2 for dividing the output signal of the conversion unit 1 to 4, and the above-described primary division unit Phase comparison between the filter unit 3 for high pass filtering the output signal of (2) and outputting only high frequency, and the output signal of the filter unit 3 and the signal fed back through the secondary frequency divider 5 is performed at 14,318 l8 MHz. A phase synchronizing unit 4 for generating a clock having a frequency of? And a secondary frequency divider 5 for feeding back the phase synchronizing unit 4 to the phase synchronizing unit 4 by dividing the output signal of the phase synchronizing unit 4 into 16; Clock generation circuit for an image memory, characterized in that consisting of.
KR2019860007595U 1986-05-29 1986-05-29 Picture memory clock generation circuit KR910001472Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019860007595U KR910001472Y1 (en) 1986-05-29 1986-05-29 Picture memory clock generation circuit

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Application Number Priority Date Filing Date Title
KR2019860007595U KR910001472Y1 (en) 1986-05-29 1986-05-29 Picture memory clock generation circuit

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KR870019326U KR870019326U (en) 1987-12-28
KR910001472Y1 true KR910001472Y1 (en) 1991-03-04

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