KR910000535Y1 - Dc voltage limiting circuit using damp pulse - Google Patents

Abstract

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Description

DC voltage limit circuit using clamp pulse

1 is a circuit diagram of a DC voltage limit circuit using the present invention clamp pulse.

* Explanation of symbols for main parts of the drawings

A: Blanking pulse B: DC regeneration circuit

C: Video output circuit d: Clamp generation circuit

TR1-TR5: Transistor R1-R6: Resistor

C1-C3: capacitors D1, D2: diodes

The present invention relates to a DC voltage limiting circuit using clamp pulses in a color amplification circuit of a color monitor or TV, and increases or decreases the clamp pulse voltage when faithfully reproducing image quality by applying a clamp pulse in a video color amplification circuit of a patent color monitor or TV. The present invention relates to a DC voltage limiting circuit using a clamp pulse to detect and detect and limit a DC voltage of an image amplifying circuit to a constant level.

Conventional color monitors or TVs have only a function of applying a clamp pulse, so that a clamp pulse is generated using a blanking pulse and the pulse is applied to an image amplification circuit.

Therefore, when the clamp pulse level is changed, the bias of the transistor of each amplification circuit is changed, which damages the components of each circuit, resulting in a problem of equipment failure.

In order to solve the above problems, the present invention can control the bias voltage constantly by reducing the changed voltage immediately by the control circuit when the bias voltage changes due to the change of the clamp pulse level. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The blanking pulse (a) is applied to the DC regeneration circuit (C) and the image output circuit (D) through a clamp generating circuit (B) composed of resistors (R1) transistors (TR2) and TR1 to improve image quality. In the image amplification circuit, the clamp generating circuit (B) and the emitter terminal of the transistor TR1 are composed of a resistor (R12-R6) diode (D1-D2) and a capacitor (C1-C3) transistor (TR3-TR5). When the DC voltage limiting circuit (e) is connected to explain the effect of the present invention configured as described above is as follows.

First, when power is applied to the circuit and the blank pulse is applied to the base of the transistor TR2 through the resistor R1, the transistor TR2 is turned on and thus the power supply voltage applied to the collector terminal of the transistor TR2. (B ⁺ ) is applied to the base terminal of the transistor TR1 via its emitter terminal. Therefore, since the transistor TR1 is turned on, the collector terminal of the transistor TR1 is subjected to a clamp pulse to the direct current regeneration circuit (C) with the waveform being out of phase with the base. When the clamp pulse is normally input as described above, since the voltage applied to the emitter of the transistor TR1 is low, the power supply voltage B + dropped by the resistor R2 is turned on through the diode D1 and the transistor TR4 is turned on. However, since the voltage across the emitter terminal of the transistor TR4 is also low, the base voltage of the transistor TR3 is also lowered so that the transistor TR3 does not operate while the transistor TR5 has a resistor R3 and a diode ( Since the collector voltage of the transistor TR4 through D2) does not drop significantly, current is flowed from the emitter terminal to the collector terminal because a divided voltage is applied to the base terminal of the transistor TR5 by the resistors R5 and R6. It will work.

That is, in the steady state, only the transistors TR4 and TR5 are operated, and the transistor TR3 is turned off.

On the other hand, since the clamp pulse is increased due to the internal change of the circuit, and the voltage applied to the base of the transistor TR1 of the clamp generating circuit is large, the current flowing from the collector to the emitter increases, thereby increasing the voltage of the emitter.

Since the increased voltage is applied to the base terminal of the transistor TR4 through the diode D1 of the DC voltage limiting circuit (e), the transistor TR4 is turned on so that the power supply voltage B + is the resistor R3 diode D2. Since the collector terminal and the emitter terminal of the transistor TR4 flow out, the voltage across the emitter terminal of the transistor TR5 is lower than the voltage across the base terminal, so the transistor TR5 is turned off. Therefore, since the current flowing from the collector terminal of the transistor TR4 to the emitter terminal is applied to the base terminal of the transistor TR3, the transistor TR3 is turned on and the clamp pulse increased from the clamp generating circuit C is increased. Since the DC level is kept constant by dropping the voltage, the clamp pulse is prevented from changing due to the change in the circuit and the DC level is not changed.

As described above, the present invention connects the DC voltage limiting circuit composed of transistors to the image amplifying circuit to improve the image quality by applying the clamp pulse to the DC regeneration circuit and the image output circuit. It prevents the DC level from changing and keeps it constant at all times, and prevents the image quality from changing according to the clamp pulse applied to the image amplification circuit. It can provide an effect.

Claims (1)

Blanking pulse (a) is applied to DC regeneration circuit (C) and image output circuit (E) via clamp generating circuit (B) consisting of resistor (R ₁ ), transistor (TR ₁ ), (TR ₂ ) according to the video amplifier circuit so as to improve, when the power source voltage (B ⁺⁾ of this capacitor (C3), (C2) and a resistor (R5), is applied to the base via the (R6) back resistor (R ₃₎ Connected to the collector of the NPN transistor TR ₄ from the emitter of the PNP transistor TR ₅ to be applied as an emitter, and the base connected to the emitter of the transistor TR ₄ via a resistor R ₄ . The collector of transistor TR ₃ is connected to the base of transistor TR ₄ and connected to the power supply terminal B ⁺ via diode D ₁ , capacitor C ₁ , and resistor R ₂ . a DC voltage-limiting circuit (e) connected to the emitter in the transistor (TR ₁₎ of the clamp generating circuit (B) remains constant A clamp pulse, characterized by being configured to maintain the DC level of the DC voltage circuit using jehwan.