KR900008456B1 - Video encoding apparatus - Google Patents

Abstract

No content.

Description

Vector quantization encoder

1 is an overall configuration diagram of a conventional image encoding apparatus.

2 is an explanatory diagram for explaining the principle of general vector quantization.

3 is a diagram showing the positional relationship between an input block and a plurality of blocks that are subject to distortion calculation in a conventional image encoding apparatus.

4 is a block diagram showing the configuration of a vector quantum encoder, which is the whole technique of the first embodiment of the present invention.

Fig. 5 is a block diagram showing the construction of the first embodiment of this invention.

6 is a block diagram showing the detailed configuration of the main elements of the first embodiment.

7 is a block diagram showing an example of a wood search vector quantization coder as a prerequisite of the second embodiment of the present invention.

FIG. 8 is a configuration diagram showing an example of the second stage of the wood search vector quantization coder as a prerequisite of the second embodiment. FIG.

9 is a block diagram showing an embodiment of a wood search vector quantization encoder according to a second embodiment of the present invention.

FIG. 10 is a block diagram showing an embodiment of a second stage of the Seek vector quantization encoder according to the second embodiment of the present invention. FIG.

11 is an address map display diagram of output vector code tables # 0 and # 1 according to the second embodiment of the present invention.

FIG. 12 is an explanatory diagram of search in quantum search vector according to the second embodiment of the present invention. FIG.

13 is a block diagram showing an inter-frame vector quantization coder as a prerequisite of the third embodiment of the present invention.

14 is a block diagram showing an inter-frame vector quantization coder as a third embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

310: prescan vector quantization unit 320: distortion determination circuit

330: variable length coding circuit 420, 440, 460: encoder

500: vector quantizer

The present invention relates to, for example, a vector quantization encoding apparatus applied to a video communication system.

Conventional devices of this kind, in particular, a motion compensation image coding apparatus, are shown in FIG.

In Fig. 1, 1 is an A / D converter, and this A / D converter 1 inputs an image signal output from the video camera 8 and outputs it by analogue / digital conversion.

2 is a block configuration unit, and inputs a digital signal sequence output from the A / D converter 1 to block and output pixels K (K is an integer of 2 or more) adjacent to each other on the image.

3 is a frame memory, which stores data one frame before the frame of the current input signal given through the adder 10. FIG.

4 denotes a plurality of blocks formed by a signal sequence of one frame before, including a block coming at the same position on an input block image including the current input signal sequence blocked by the block structure unit 2; Read by the frame memory (3).

5 is a distortion calculation unit which calculates the distortion of the signal sequence of the input block outputted from the block constitution unit 2 and the signal sequence of the plurality of blocks stored in the frame memory 3 and gives the position information of the block which gives the least distortion, and The signal sequence at this point is output.

6 is a subtractor and obtains and outputs a vector of a signal sequence of an input block output from the block constructing unit 2 and a difference signal sequence of a signal sequence of a block giving a minimum distortion output from the distortion calculating unit 5.

7 is a quantization encoder and is configured to receive a vector of the difference signal sequence outputted from the subtractor 6 and to quantize it.

9 is a quantization decoding unit that reproduces the electric difference signal sequence from the quantized coded signal output from the quantization coding unit 7.

10 is an adder, which adds the quantized decoding output from the quantization decoding section 9 and the signal sequence of the block giving the least distortion output from the distortion calculating section 5 to reproduce an image signal, and writes it to the frame memory 3. It is supposed to be.

Here, the principle of vector quantization will be briefly described with reference to FIG.

Information source Input signal sequence K is summed and input vector X = [X ₁ , X ₂ ,. X _K ].

의 N개의 대표점(즉 출력벡터)

의 세트를

로 한다. 출력벅터

를 대표점(예 : 중심)으로 하는 RK의 각 분할을 R1, R1R倻 면 벡터 양자화 Q는 다음식으로 정의된다.At this time, K-dimensional Euclit signal space

N representative points of (ie output vector)

Set of

Shall be. Output Bucket

For each division of RK whose representative point is (eg, center), R1, R1R 'plane vector quantization Q is defined by the following equation.

Q: R ^K ? … … … … … … … … … … … … … … … … … … … … … … … … … … (One)

………………………………(2)here

… … … … … … … … … … … … (2)

The vector quantization Q is represented as a cascade of coding C and decoding D.

의 인덱스세트 I=1, 2, …, N〕로의 사상(寫像)이며 복호화 D는 I로부터 Y의 사상이다.Code C is the set of output vectors of RK

Set of indexes I = 1, 2,... , N], and decoding D is from I to Y.

That is, C: R ^K → I, O: I → Y... … … … … … … … … … … … … … … … … … … … … (4)

Q = D · C... … … … … … … … … … … … … … … … … … … … … … … … … (5)

to be.

In vector quantization, the encoding efficiency is extremely good because the electrocoded output I is transmitted or recorded.

Vector quantization maps the input vector to the output vector yi at the shortest distance (minimum distortion).

Specifically, if the distance (distortion) between the input and output vectors is d (x, yi), it is as follows.

)＜d(

) 모든 j에 대하여 ………………………………………(6)if d (

) <D (

) For all j… … … … … … … … … … … … … … … (6)

(-R; 즉

→

………………………………………………………………(7)

(-R; i.e.

→

… … … … … … … … … … … … … … … … … … … … … … … … (7)

The set Y of the output vector yi as shown in FIG. 3 is clustering using an input source signal sequence that is a training model (the selection of representative points and the division of the signal space are minimized. Can be repeated until

The operation of the configuration of FIG. 1 will be described below.

The image signal output from the video camera 8 to the A / D converter 1 is converted into a digital signal sequence by the A / D converter 1 and output to the block constitution unit 2. The digital signal sequence is blocked in the block structure section 2 so as to have a rectangular (or square) shape for every K adjacent pixels on the image, and at the same time converts the sequence of the signal sequence to distort the calculation unit 5 and the subtractor ( 6) is output.

On the other hand, the signal sequence of the electric plural blocks stored in the frame memory 3 and read by the reference signal generation section 4 is outputted from the block configuration section 2 by the reference signal generation section 4. It is sent to the distortion calculation unit 5 in synchronization with the signal sequence.

An example of the positional relationship between a block of the current input signal sequence output from the block constitution unit 2 and a plurality of blocks read by the reference signal generator 4 is shown in FIG. As shown in the frame.

The distortion calculation of the signal sequence of the current input block and the signal sequence of the plurality of blocks described above is performed in the distortion calculation unit 5 using, for example, Euclid distortion or absolute value distortion.

Based on this calculation result, a block giving the least distortion to the current input block is selected from the plurality of blocks.

If the number of blocks to be calculated is M (M is an integer of 2 or more), and the block giving the least distortion is a double L-th (L = 1, 2, ... M), the distortion calculation unit 5 The value of l and the signal sequence of this block are output to the subtractor 6.

Based on the signal sequence of the input block and the signal sequence giving the minimum distortion, the subtractor 6 obtains the vector of these difference signal sequences and outputs it to the quantization coding 7.

The vector of the difference signal sequence is quantized coded in the quantization encoder 7 and output to the quantization decoder 9.

The difference signal sequence reproduced by the quantization decoding section 9 and the signal sequence of the block giving the electrical minimum distortion output from the electrical distortion calculating section 5 are respectively output to the adder 10 and added by the adder 10. And reproduced as an image signal.

This image signal is recorded by the electric adder 10 in the frame memory 3.

The signal processing in the process from the quantization encoder 7 to the adder 10 described above relates to post-processing by a vector of electric vehicle signal sequences obtained by the subtractor 6, namely the magnitude of the difference signal. The smaller the vector amount, the higher the efficiency of motion compensation.

The image signal input as described above is blocked and encoded by quantizing the information of which position of the frame one frame before the current image signal is most similar to and the error component thereof.

The conventional image encoding apparatus, in particular, a motion compensation image encoding apparatus, is constructed as described above, and is a frame memory which is subject to distortion calculation even when the screen movement direction is obvious due to a movement such as a video rotation of the video camera 8 ( Since the positional relationship between the block stored in 3) and the input block output from the block forming unit 2 is fixed, there is a problem that the efficiency of motion compensation cannot be improved.

A first object of the present invention is to provide a vector quantization encoder that can significantly improve coding efficiency.

A second object of the present invention is to provide a vector quantization encoder capable of commonizing the contents of the contents constituting the output vector code table of each stage.

Since access addresses of the memory constituting the code table are duplicated at each stage, it has been impossible to make it possible, and the contents of the storage are required (at least at each stage).

A third object of the present invention is to obtain an inter-frame vector quantization encoder capable of band-compression of an image signal with high image quality by reducing noise on a block in an image signal.

The first object is a pre-scan vector quantization unit for reading a multi-dimensional signal space including an input signal vector from an output vector set of each representative point divided into a plurality of points and searching for the output vector having a minimum distortion relation with the input signal vector. And a distortion determining circuit which can set an allowable distortion and generates a significant signal by judging that the distortion between the input vector and the output vector is less than or equal to the allowable distortion, and the output at the time when the distortion determining circuit generates the significant signal. It is realized by having a variable length coding circuit for variable length coding the index signal of the vector to generate a coded output.

The second object is provided with an encoder which calculates a distortion of each output vector index and an input signal vector stored in the vector code table and obtains an output vector index whose minimum is the distortion. Among the output vector indexes of the previous coding stages, an initial pseudo output vector index in which the indexes of the pseudo-output vectors whose code lengths match with the zero sign is added to the upper part of the output vector index with the shorter code length as necessary. A vector code table that is input and held by the encoder of each stage is realized by pairing the pseudo output vector index with an output vector corresponding to the initial pseudo output vector index.

The third object is to compare the difference between the input image signal sequence and the image signal sequence before one frame period as the prediction signal sequence, and compare the difference signal with a threshold set by the feedback control signal from the transmission buffer. It is realized by determining, blocking only the effective pixels, performing mean-length separated normalized vector quantization coding, variable length coding, and outputting the coded output thereof by transmission buffer.

Hereinafter, each Example of this invention is described.

However, before describing the detailed description of each embodiment, the outline of each embodiment will be conceptually described, and the configuration and operation thereof will be described.

Prior to the description of the first embodiment, the entire description thereof will be described with reference to FIG.

4 is a block diagram showing the configuration of the vector quantization coder of the premise technique of the first embodiment, where 101 is an input vector register for holding an input signal sequence blocked, and 102 is a code table address for creating an address of a code table. A counter 103 denotes an output vector code table memory for storing an output vector, 104 an output vector code table register for holding data read from the output vector code table memory, and 105 a value of an input vector register 101 and an output vector. A parallel subtractor for calculating the difference from the value of the code table register 104, 106 a parallel absolute value calculator for calculating the absolute value of the output of the parallel subtractor, 107 an absolute distortion detector for detecting absolute distortion of the input / output vector, and 108 an input / output Minimum distortion detector for detecting an output vector with minimum absolute distortion of the vector, 109 is a minimum distortion detector Based on the output signal of 108, the index latches holding the indices of the output vectors with the minimum distortion are displayed.

Next, the operation will be described.

=〔x₁, x₂, …, x_k〕로 하여 입력벡터 레지스터(1)에 등록한다. 이 시점에서 코드테이블 어드레스 계수기 (102)에 대하여 i=1, 2,…,N까지 순차 계수시켜서 순번으로 출력벡터

=〔yi₁, yi₂,…, yi_k〕를 출력벡터 코드테이블 메모리(103)으로부터 판독하고 출력벡터 코드테이블 레지스터(104)로 래치(latch)한다.The input vector of the encoder is blocked by adding up the K number of input vectors.

= [X ₁ , x ₂ ,... , x _k ] is registered in the input vector register (1). At this point, i = 1, 2,... For code table address counter 102. Output vector sequentially by counting up to N

= [Yi ₁ , yi ₂ ,... , yi _k ] is read from the output vector code table memory 103 and latched to the output vector code table register 104.

For each output vector yi, the parallel subtractor 105, the parallel absolute value calculator 106, and the absolute distortion detector 107 obtain the absolute value di of the input / output vector by the following operation.

Next, the minimum distortion detector 108 detects the output vector whose absolute distortion di is minimum.

Minimum distortion d is

to be.

과 입력벡터

의 왜곡 d(

)를 계산하여 과거의 최소치와 비교하여 보다 작은 값이 검출될 때 이것을 새로운 최소왜곡으로서 보존하여 그때마다 스트로브(strobe)신호를 인덱스 래치(109)에 송출하여 출력벡터의 코드테이블 어드레스인 인덱스신호 i를 인덱스 래치(109)로 송신한다.The minimum distortion detector 108 is an output vector sequentially read from the output vector code table memory 103.

And input vector

Distortion of d (

) Is calculated and stored as a new minimum distortion when a smaller value is detected compared to the past minimum value, and a strobe signal is sent to the index latch 109 every time, and the index signal i which is the code table address of the output vector is calculated. Is sent to the index latch 109.

가 전부(i=I-N)판독될때까지 계속되어 전체탐색이 완료된다.The procedure is an output vector from the output vector code table memory 103.

Continues until all (i = IN) has been read, completing the full search.

At this point, the index i of the output vector, which becomes the minimum distortion, remains in the index latch 109, which becomes a code output.

The above is the prescan vector quantization unit constituting the vector quantization coder.

Next, the first embodiment will be described.

In this embodiment, the allowable distortion is set in the distortion judging circuit, and the variable length coding of the index signal of the output vector is performed when the distance (distortion) between the input vector and the output vector becomes less than the allowable distortion during the search of the output vector of minimum distortion. Encoding efficiency is improved by obtaining the encoding output.

dθ로된 시점에서 출력벡터의 인덱스신호 i를 가변길이 부호화하여 부호화출력을 얻는 가변길이 부호화회로이다.FIG. 5 is a block diagram showing the structure of this first embodiment, and 310 is a pre-scan vector quantization unit having the same configuration as that described in FIG. 4 (hereinafter, referred to as the FSVQ unit including the entirety of FIG. 4). Is a distortion determining circuit for determining that the absolute distortion di is less than or equal to a predetermined allowable distortion dθ, and 330 is an absolute distortion di and an allowable distortion dθ based on the output of the distortion determining circuit.

A variable length coding circuit that obtains a coded output by variable length coding the index signal i of the output vector at the point of dθ.

6 is a block diagram showing the detailed configuration of the FSVQ section 310 of this embodiment, and the same reference numerals as in FIG. 4 denote the same elements.

The code table address counter 102, which can be reset by the output of the distortion determining circuit 320, is used instead of the code table address counter 102 in FIG.

The operation of this embodiment configured as described above will be described below.

=[x₁, x₂…x_k〕로서 FSVQ부(310)에 입력된다.First, the input signal sequence of the encoder is blocked by combining K pieces of input signals.

= [x ₁ , x ₂ ... x _k ], is input to the FSVQ unit 310.

를 입력벡터 레지스터(101)에 등록하는 한편 재세트 기능부 코드테이블 계수기(102)에 대하여 순서대로 i=1∼N까지 계수시킴으로써 출력벡터 yi=〔yi·₁, yi·₂, …, yi·_k〕를 출력벡터 코드테이블 메모리(103)에서 판독하여서 출력벡터 레지스터(104)에 순차 래치시킨다.In the FSVQ section 310, the input vector

Is registered in the input vector register 101 and counts from i = 1 to N in order with respect to the code table counter 102 of the reset function unit, and output vector yi = [yi · ₁ , yi · ₂ ,... , yi · _k ] are read from the output vector code table memory 103 and sequentially latched to the output vector register 104.

와 각 출력벡터

과의 절대치 왜곡 di를 구한다.Next, the parallel vector 105 is obtained by the parallel absolute value calculator 106 and the absolute distortion detector 107 as shown in the following equation.

And each output vector

Find the absolute distortion di with.

The minimum distortion detector 108 compares the absolute value distortion di with the minimum value in the past and, when a smaller value is detected, accepts it as a new minimum distortion value and outputs it to the distortion determination circuit.

의 코드테이블 어드레스인 인덱스신호 i를 인덱스래치(109)로 송신하여 가변길이 부호화회로(330)으로 출력한다.Each time, the latch signal is sent to the index latch 109 to output the latch.

The index signal i, which is a code table address of, is transmitted to the index latch 109 and output to the variable length encoding circuit 330.

di의 관계가 성립한 시점에서 가변길이 부호화회로(330)로 인덱스래치신호를 발신하여 인덱스신호 i를 수신시킨다.The above procedure is executed whenever the counter of the reset function code table address counter 102 is counted from i = 1 to N, but the distortion determination circuit 320 receiving the output di of the minimum distortion detector 108 is previously Dθ compared to the set allowable distortion dθ

When the relation of di is established, the index latch signal is sent to the variable length coding circuit 330 to receive the index signal i.

A reset signal is sent to the code table address counter 102 of the reset function unit to terminate the count and reset it to i = 1.

The variable length encoding circuit 330 receiving the index signal i deletes all "0s" that continue from the most significant bit to the least significant bit of the index signal i and shortens the code length.

This procedure is performed for all of the received i parts to perform variable length coding to obtain encoded output.

및 출력벡터

의 왜곡 di와 설정된 허용 dθ를 비교하여 di

dθ로된 시점에서 탐색을 중지함과 동시에 그때의 출력벡터의 인덱스신호 i를 가변길이 부호화하여 부호화 출력으로하고 있으므로 부호화 효율이 대폭 향상되며 이에 의하여 고속처리가 실현된다.This embodiment is an input vector as described above.

And output vectors

Compares the distortion di and the set allowable dθ

Since the search is stopped at the point of dθ and the index signal i of the output vector is subjected to variable length coding to be coded output, the coding efficiency is greatly improved, whereby high-speed processing is realized.

Prior to the description of the second embodiment, a description will be given of the tree search vector quantization, which is the entire technique.

As shown in Fig. 12, considering the binary tree where two branches branch from each branch point R, the roots correspond to the K-dimensional signal space R ^K and each branch point corresponds to the space obtained by dividing the space R ^K stepwise.

Representative points (eg centers) are defined in each space, and the electrical representative point becomes the output vector in K-dimension.

Based on the distribution of the output vector and input vector of each stage, it is calculated | required so that the verticalization of the distortion between input / output vectors may be minimum. Given an input vector, the output vector corresponding to the termination branch is selected by comparing the distortion with the output vector corresponding to the two branching points branching from the first stage to the final stage. If the last stage is the n-th stage, there are 2n termination points.

The above is a description of the tree search vector quantization (TSVQ). In Fig. 12, an example of n = 3 is shown.

7 shows an example of the configuration of the tree search vector quantizer in the case of n = 3. In FIG. 7, V ₁ denotes an input signal vector blocked for every K pieces, 420 denotes a first stage of the TSVQ encoder to which the input signal vector is input, and V ₃ denotes a first stage output vector index output from the first stage of the TSVQ encoder, 440. Is the second stage of the conventional TSVQ encoder to which the first stage output vector index is input, V ₅ is the second stage output vector index to be output from the second stage of the TSVQ encoder, and 460 is the TSVQ encoder to which the second stage vector output index is input. The third stage V ₇ is a third stage output vector index output from the third stage of the TSVQ encoder.

8 shows an example of the configuration of the second stage 440 of the TSVQ encoder.

In FIG. 8, 441 is an input vector register to which an input signal vector V ₁ is input, 442 is a second output vector code table to which a first output vector index V ₃ is input, and 443 is an input output from an input vector register. A distortion calculation circuit for calculating a distortion between the signal and the output vector index output from the second stage output vector code table 442, 445 is a distortion comparison circuit for obtaining a minimum value of the distortion calculated by the distortion calculation circuit 443, V ₉ Is a distortion comparison result signal output from the distortion comparison channel 445, and 446 is an index register for outputting the second output vector index V ₅ based on the distortion comparison result signal V ₉ and the signal V ₃ of the first output vector index. to be. Next, the operation will be described.

Throat search vector quantization is an iteration of comparing the distortion of two paired output vectors and input vectors at each stage and determining the paired output vectors to be compared at the next stage.

The three-step distortion operation of the neck shown in FIG. 12 corresponds to the first stage 420 of the TSVQ encoder, the second stage 440 of the TSVQ encoder, and the third stage 460 of the TSVQ encoder of FIG. . At each stage, the distortion of the output vector pair and the input vector designated by the distortion comparison result up to the front end is determined and the smaller one of the distortion is determined. The information is added to the comparison result up to the front end and sent to the next stage.

Since there is only one pair of output vectors in the first stage, the comparison result up to the front end is unnecessary and does not exist.

If the output index V ₃ outputted as a result of the distortion comparison in the first stage is i ₁ , the second stage performs a distortion operation on the input vector pair and the input vector determined by i ₁ , and compares the result with i ₁ . In addition to form i ₂ 5. In the third stage, i ₂ and i ₂ 7 are output by the input.

In FIG. 12, if the branch on the left is selected, 0 is assigned, and if the branch on the right is selected, 1 is assigned. The index i ₁ , i ₂ , and O ₃ become a binary string of 1, 2, and 3 digits, respectively. The vector i ₃ of this binary string becomes the output vector index of the last stage.

This concludes the description of the motion vector quantizer.

Here, the output vector code table in each stage is a pair of output vectors designated by the front end result, as shown in FIG. 11, y ₀ , y ₁ in the first stage, y ₀ , y ₁ , y ₁₀ , y in the second stage. _In the third and third stages, y ₀ , y ₁ , y ₁₀ , y ₁₁ , y ₁₀₀ , y ₁₀₁ , y ₁₁₀ , and y ₁₁₁ must be stored as the output vector indices.

A second embodiment will be described below.

One of the output vector indices stored in the vector code table at the first stage of the encoder is selected based on the initial pseudo output vector index and the input signal vector inputted at the first stage of the encoder, and the first stage output vector index is output at the first stage of the encoder. In addition, a pseudo output vector index and an input signal vector distortion obtained by matching a zero-code length above a short output vector of a code length are calculated by a calculation circuit. As a result, the vector code table holding the encoders of each stage can be shared.

9 to 11 illustrate the case where the initial pseudo index is " 1 " (BIN) in the search step 3 as the second embodiment. FIG. 9 is a block diagram in which the search stage of the tree search vector quantization encoder according to the embodiment has three stages, and the same parts as in FIG.

In FIG. 9, V ₄ denotes an initial pseudo output vector index, 420 denotes an initial pseudo output vector index V _4, and an input signal vector of the TSVQ encoder according to the present embodiment. V ₆ denotes a first stage of the TSVQ encoder. The first stage pseudo-output vector index outputted from 420, 440 is the second stage of the TSVQ encoder to which the input signal vector V ₁ and the first stage pseudo-output vector index V ₆ are input, and V ₈ is the second stage 440 of the TSVQ encoder. The output second stage pseudo-output vector index 460 is the third stage of the TSVQ encoder to which the input signal vector V ₁ and the second stage output vector index V ₈ are input.

FIG. 10 is a block diagram showing, in FIG. 9, the second stage of the TSVQ encoder according to this embodiment in more detail.

In FIG. 10, the output vector code table 442 of the second stage 440 of the TSVQ encoder has a second output vector code table # 0 and a second output vector code table # 1.

The input signal vector V ₁ is input to the distortion calculation circuit 443 through the input signal vector register 441, and the distortion calculation circuit 443 is provided with the second output vector code table # 0 and the second output vector code. the result of this calculation to calculate the vector index to the input signal and the distortion of the vector V ₁ stored in the table # 1 is input to the second stage distortion comparator (445).

The second stage distortion comparator 455 is the output of distortion comparison result signal V ₉ of 0 or 1 by the calculation result, and it inputs in the distortion comparison result signal V9 and the output vector code table 442, the first stage pseudo Unlike the output vector index V ₆ , the pseudo index shift register 446 outputs the second stage pseudo output vector index V 8. Here, the TSVQ encoder first stage 420, the TSVQ encoder second stage 440, and the TSVQ encoder 460 constitute the vector quantization apparatus 500 as a whole.

Next, the case where the initial pseudo index is set to "1" (BIN) in the above-described operation of this embodiment will be described. First, an address map in the case where the search of the output vector code tables # 0 and # 1 common to the respective search ends is performed in three stages is shown in a table of FIG.

The distortion of the vector signal y0 and y1 output from the output vector code tables # 0 and # 1 by the input signal vector 1 input to the first stage of TSVQ and the initial pseudo output vector index V4 " 1 " Calculated in circuit 443. The distortion comparison channel 445 selects one output vector to be the minimum valley according to the calculation result of the distortion calculation circuit 443, and outputs the distortion comparison result signal V ₉ based on the selected result.

The pseudo index shift register 446 adds the distortion comparison result signal V ₉ to the least significant digit LSB of the first stage pseudo output vector index V ₆ , and truncates the most significant digit MSB and the second stage pseudo output vector index to the next stage. Send to.

By this the same operations carried out the second stage, third stage third stage pseudo the nearest physician lowest digit LSB "1" of the output vector index in the index shift register all well rear obtain the third to obtain a single Multi V ₇ have.

Specifically, in the first stage of the TSVQ encoder for the input vector, the initial pseudo output vector index "1" (BIN) indicates that the vector index y0 in the output vector code table # 0 and the vector index y1 in the output vector code table # 1 are represented. If that is output the output vector code table # 0 vector index y0 selects the distortion comparison result signal V ₉ is in "0", the pseudo index shift register 446 of the initial pseudo output vector index V ₄ "1" (BIN) The least significant digit LSB "0" is added and the most significant digit MSB is "0" removed.

This is expressed as the following formula.

001 (BIN) → 0010 (BIN) → 010 (BIN)

In the second stage of the TSBQ encoder, the output vector y ₀ is output from the output vector code table # 0 and the vector index y ₁ is output from the output vector code table # 1 by the first stage pseudo-output vector index V ₆ "10" (BIN). vector code table # ₁ is selected if the first vector index y of the second stage pseudo output vector index V ₈ is

010 (BIN) → 0101 (BIN) → 101 (BIN)

Becomes

In the third stage of the TSVQ encoder, the vector indexes y ₁₀ and y ₁₁ are outputted by the output vector code tables # 0 and # 1 by the second stage pseudo-output vector index V ₈ "101" (BIN). When the vector index y ₁₁ of 1 is selected, 101 (BIN)-&gt; 1011 (BIN)-&gt; 011 (BIN), and the initial pseudo output vector index disappears, and the index "11" (BIN) of the vector index y011 is the third stage output vector index. Is obtained as (signed output) 7.

This search process is consistent with the route in FIG. As described above, according to this embodiment, the encoder of the first stage of each encoder adds a vector index having a shorter code length among the output vector indices of each encoder and a pseudo-output vector index whose code length is adjusted by adding zero code to the upper position. The vector code table held by the encoder of each stage is inputted while the initial pseudo output vector index, which is not duplicated, is constructed by matching the pseudo output vector index with the initial pseudo output vector index. It can make common and reduce the contents of memory.

Prior to the description of the third embodiment, the premise will be described with reference to FIG. In FIG. 13, the same reference numerals as in FIGS. 1 to 12 denote the same or upper portions.

s _g1 is an image signal, 6 is a subtractor, 3 is a frame memory, 511 is a transmission buffer, 7 is an average separated normalized vector quantizer, s _g2 is a quantized output, 517 is a variable-length coder, s _g3 is an encoded output, and 9 is an average Separate normalized vector quantization decoder, 522 is a raster / block scan converter, 523 is an image signal block, 524 is a preliminary signal block, 525 is a prediction error signal block, 526 is a prediction error signal block, 527 is a reproduction image The signal block s _g4 is a feedback control signal.

Next, the operation of the inter-frame vector quantization encoder shown in FIG. 13 will be described. The image signal s _g1 is a signal sequence which is digitized and given in the order of the raster scanning direction.

The raster / block scan converter 522 divides the image signal s _g1 into K blocks (K is an integer) and scan-converts them in the order of the blocks.

, 재생화상신호블록(527)을

, 프레임메모리(3)에 의하여 1프레임주기의 지연을 받은 재생화상신호블록(527)로서 얻어지는 예측신호블록(524)를 pf로 하면 아래와 같은 식이 성립된다.It is assumed that the image signal block 523 blocked in the f- _th frame is represented by the signal source vector sf = (S ₁ , S ₂ ,... S _k ). In addition, the prediction error signal block 525, which is the difference between the image signal block 523 and the prediction signal block 524, calculated by the subtractor 6, is divided into an ef average separated normalized vector quantization encoder 7 and an average separated normalized vector quantized decoder. The reproduction prediction error signal block 526 formed by (9)

, The playback picture signal block 527

When the prediction signal block 524 obtained as the reproduction picture signal block 527 subjected to a delay of one frame period by the frame memory 3 is pf, the following equation is established.

Q denotes a vector abbreviation error, and z ^−t denotes a delay of one frame period by the frame memory 3.

This is basically a DPCM method (differential pulse modulation method) between frames. The quantized output s _g2 of the mean value separated normalized vector quantizer encoder 7 is variable length coded by the variable length encoder 517, is sent to the transmission buffer 511, and is output to the transmission path as the encoded output s _g3 .

The transmission buffer 511 monitors the amount of transmission information and controls the amount of encoded data by controlling the threshold value in the average separated normalized vector quantization encoder 7 according to the feedback control signal s _g4 .

In addition, the average separated normalized vector quantization encoding is Japanese Murakami Togumichi, Asai Mitsuda, Eisen Yamasaki's 6th Information Theory and his applied research paper (1983), pages 77-82. As described in "Performance Coding" (Document 1) and Japanese Television Society published in Japanese Muragami Togumichi and Mitsuda Asai (1984) on pages 452-457, "Vector Quantizer of Image Signals (Document 2)" Description is omitted.

A third embodiment will be described below. In the inter-frame vector quantization encoder of this embodiment, the validity of the prediction error signal sequence that is the difference between the frames of the image signal is determined to be invalid. Image noise is reduced and image transmission is realized with high image quality.

Fig. 1 is a block diagram showing an inter-frame vector quantization encoder as one embodiment of the present invention. In Fig. 14, the same reference numerals as in Figs. 1 to 12 denote the same or corresponding parts.

3 is a frame memory, s _g5 is a prediction signal sequence, s _g6 is a prediction error signal sequence, 560 is a rasterization circuit, s _g7 is a reproduction prediction error signal sequence, s _g8 is a reproduction image signal sequence, and 590 is a valid / invalid decision circuit. , 510 is a block circuit, 511 is a transmission buffer, s _g9 is a feedback control signal, s _g10 is valid / invalid information, s _g11 is a block signal, 7 is a mean separated normalized vector quantization coder, s _g2 is a quantization output, and 517 is variable. The length coder, s _g3 is the coded output, 9 is the mean separation normalized vector quantized decoder, s _g12 is the playback block signal, and 10 is the asset.

Next, the operation of the interframe vector quantization encoder as one embodiment shown in FIG. 14 will be described.

로 하며 재생화상 신호계열 s_g8을

로하고 프레임메모리(3)에 의하여 1프레임주기 지연된 재생화상신호계열로서 얻게되는 예측신호계열 s_g5를 Prf로 하면 다음같은 식이 성립된다.The difference between the input signal sequence Srf calculated by the subtractor 6 and the Prf of the predicted signal sequence s _g5 from the frame memory 3 as the image signal s _g1 of the raster scan in the f-th frame now. The reproduction prediction error signal sequence s _g7 reproduced by the rasterization circuit 560 using the predictive error signal sequence s _g6 as erf is

Reproduction signal sequence s _g8

If the predicted signal sequence s _g5 obtained as the reproduced picture signal sequence delayed by one frame period by the frame memory 3 is Prf, the following equation is established.

Q denotes a vector quantization error, and z ^−t denotes a delay of one frame period by the frame memory 3. This is basically a DPCM method between frames.

The prediction error signal sequence 5 calculated by the subtractor 6 in the DPCM system between such frames is input to the valid / invalid decision circuit 590 and the block circuit 510. The valid / invalid determination circuit 590 sets the threshold value according to the feedback control signal s _g9 from the transmission buffer 11 and outputs valid / invalid information s _g10 (e.g., valid is "1", invalid is "0"). do.

The blocking circuit 510 receives the prediction error signal sequence s _g6 and the valid / invalid information s _g10 and combines only K pixels (K is plural) which are determined to be valid, so that the block signal s _g11 is x = (x ₁ , x ₂ , ..., x _k ). If the number of effective pixels in one frame is not a multiple of K, dummy data (e.g., "0") is inserted to form one block.

The average value-separated normalized vector quantization coder 7 having received the block signal s _g11 quantizes the block signal s _g11 by an average value and a dispersion index to obtain a quantization output s _g2 .

The variable length encoder 517 performs variable length coding on the quantized output s _g2 and the valid / invalid information s _g10. For example, the valid / invalid information s _g10 is run length encoded and the quantized output s _g2 is respectively. For data with a high frequency of appearance, a code having a shorter code length is assigned. On the contrary, a data having a shorter frequency is assigned a longer code.

The transmission buffer 511 which inputs these codes outputs the codes to the transmission path as the coding output s _g3 , and aggregates the amount of information generation in arbitrary periods (for example, frame unit and feed unit), thereby providing feedback control signals. The amount of information generated is controlled by outputting sg12 to the valid / invalid decision circuit 590.

로서 복호재생한다.The mean separation normalized vector quantization reconstructor (9) receives the reproduction block signal 20 by the quantization output sg2 quantized by the mean, variance, and index.

Decode and playback as.

의 각 성분

가 유효화소에만 할당되어 가며 무효화소에는「0」가 할당되어 재생예측오차신호계열 s_g7의

가 재생된다. 이 재생예측오차신호계열 s_g7의

와 프레임메모리(3)로부터의 예측신호계열 s_g5의

가 가산기(10)에서 가산되어 재생화상신호계열(s_g8)의

로서 프레임메모리(3)에 기억된다.Then, the rasterization circuit 560 receives the valid / invalid information s _g10 of the reproduction block signal s _g12 .

Each component of

Is assigned only to the effective pixels, and "0" is assigned to the invalid pixels to determine the reproduction prediction error signal sequence s _g7 .

Is played. The reproduction prediction error signal sequence s _g7

And the prediction signal sequence s _g5 from the frame memory 3

Is added in the adder 10 to add the reproduction picture signal sequence s _g8 .

It is stored in the frame memory 3 as an example.

In this embodiment, as described above, in the inter-frame vector quantization encoder, the prediction error signal sequence that is the difference between the frames of the image signal is judged as valid or invalid, and only the effective pixels are collected and blocked, and the average value division normalized vector quantization encoding is performed. By reducing the noise on the block in the signal, image transmission in high quality is realized.

Claims (4)

In the vector quantization encoding of the input signal vector having a plurality of input signal sequences blocked by pre-scanning, the multi-dimensional signal space including the input signal vector is read from the output vector set of each representative point divided into a plurality of the input signals. Allowable distortion can be set with the pre-search vector quantizer 310 for searching for the output vector having a relationship between the signal vector and the minimum distortion, and it is determined by determining that the distortion between the input vector and the output vector is less than or equal to the allowable distortion. A distortion judging circuit 320 for generating a signal and a variable length coding circuit 330 for variable-length encoding the index signal of the output vector at the time when the distortion judging circuit 320 generates a significant signal. Vector quantization encoding apparatus, characterized in that. Two branches branch at each branching point of each stage, and the input signal vector blocked at every ^{K into} the branching point of the K-dimensional vector space R ^K having 2 ⁿ branching points at the nth stage is inputted to this branching point. When an output vector index corresponding to a branch is input, one branch of each branch branched from this branch point is selected to output an output vector index corresponding to the branch selected, and the branch corresponding to each branch branched from the branch point is selected. An encoder having a vector code table storing an output vector and a distortion calculation circuit for calculating the distortion of each output vector index and the input signal vector stored in the vector code table and obtaining an output vector index at which the distortion is minimized. 420, 440, and 460 at each short node and are output from the encoders 420, 440, and 460 of each stage. In the vector quantization apparatus 500 for outputting the output vector index from the encoder of the next stage based on the output vector index and the input signal vector, and obtaining the output vector index output from the encoder of the last n stage, the encoder 420, ( 440) and 460, the first stage encoder does not overlap the pseudo-output vector indices in which the code lengths are matched by adding the required number of zero codes above the short output vector index of the code length among the output vector indices of the respective coding stages. Vector quantization, characterized in that the first pseudo output vector index is input and the vector code table held in the encoder of each stage matches the pseudo output vector index and the corresponding output vector of the initial pseudo output vector index. Encoding device. The vector quantization encoding apparatus according to claim 2, wherein the initial pseudo output vector index is " 1 " (BIN) only at the lowest level, and all the necessary bits are " 0 " (BIN). In an image encoding apparatus for encoding and transmitting an image signal, a prediction signal sequence (s _{g5) is used} to predict an image signal sequence before one frame period read from an input image signal sequence (s _g1 ) and a frame memory (3) capable of storing at least one frame. By the prediction error signal sequence s _g6 , which is the second difference, and the feedback control signal s _g9 from the transmission buffer 511 which outputs the code to the transmission path and aggregates the amount of information generation. Valid / invalid information is determined by comparison of the set thresholds, and valid / invalid information is generated, and the output (s _g2 ) obtained by outputting the average separated normalized vector quantized code with K (a plurality of K) of valid pixels as one block variable length coding with invalid information and outputting to the transmission path by the transmission buffer 511. the electrical separation mean normalized vector quantization coded output (s _g2) a block decoded signal (s _g12) of the On / allocated to the effective pixel by invalid information invalid pixel is "0", the reproduction prediction error signal series reproduced hayeoseo assignment (s _g7) and the predicted signal sequence (s _g5) for adding the reproduced image signal (s obtained by _g8 ) in the frame memory (3).

Images