KR900005836U - 캐쉬 메모리 클럭 제어회로 - Google Patents

캐쉬 메모리 클럭 제어회로

Info

Publication number
KR900005836U
KR900005836U KR2019880014165U KR880014165U KR900005836U KR 900005836 U KR900005836 U KR 900005836U KR 2019880014165 U KR2019880014165 U KR 2019880014165U KR 880014165 U KR880014165 U KR 880014165U KR 900005836 U KR900005836 U KR 900005836U
Authority
KR
South Korea
Prior art keywords
control circuit
cache memory
clock control
memory clock
cache
Prior art date
Application number
KR2019880014165U
Other languages
English (en)
Other versions
KR940001028Y1 (ko
Inventor
김연철
Original Assignee
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사 filed Critical 주식회사 금성사
Priority to KR2019880014165U priority Critical patent/KR940001028Y1/ko
Publication of KR900005836U publication Critical patent/KR900005836U/ko
Application granted granted Critical
Publication of KR940001028Y1 publication Critical patent/KR940001028Y1/ko

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR2019880014165U 1988-08-30 1988-08-30 캐쉬 메모리 클럭 제어회로 KR940001028Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019880014165U KR940001028Y1 (ko) 1988-08-30 1988-08-30 캐쉬 메모리 클럭 제어회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019880014165U KR940001028Y1 (ko) 1988-08-30 1988-08-30 캐쉬 메모리 클럭 제어회로

Publications (2)

Publication Number Publication Date
KR900005836U true KR900005836U (ko) 1990-03-09
KR940001028Y1 KR940001028Y1 (ko) 1994-02-25

Family

ID=19278874

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019880014165U KR940001028Y1 (ko) 1988-08-30 1988-08-30 캐쉬 메모리 클럭 제어회로

Country Status (1)

Country Link
KR (1) KR940001028Y1 (ko)

Also Published As

Publication number Publication date
KR940001028Y1 (ko) 1994-02-25

Similar Documents

Publication Publication Date Title
DE69032655T2 (de) Seitenspeicher-Steuerschaltung
FI98664B (fi) Kello
DE68924811D1 (de) Taktversorgungsschaltung.
KR890015268A (ko) 반도체 기억회로
DE69030127D1 (de) Speicherschnittstellensteuerung
GB2226900B (en) Memory timing circuit employing models
DE68925048D1 (de) Direktspeicherzugriffssteuerung
DE68927015D1 (de) Direktspeicherzugriffssteuerung
DE68920118D1 (de) Josephson-Speicherschaltung.
DE68918568D1 (de) Integrierte Speicherschaltung.
DE68925748T2 (de) Logische Schaltung
FR2638521B1 (fr) Limnigraphe electronique
FR2621737B1 (fr) Memoire en circuit integre
DE69225876T2 (de) Cachesteuerungsschaltung
KR900005836U (ko) 캐쉬 메모리 클럭 제어회로
DE68927363D1 (de) Datenübertragungssteuerungsschaltung
KR870008824U (ko) 캐쉬 메모리 제어회로
KR900010550U (ko) 시계의 알람 제어회로
KR900008727U (ko) 제빙기의 제빙제어회로
KR890024008U (ko) 메모리 지워짐 방지회로
KR890021881U (ko) 리얼타임 클럭의 칩선택 제어회로
KR900011180A (ko) 클럭 선택 회로
KR910012467U (ko) 메모리 백업회로
KR900019140U (ko) 디스플레이용 메모리 제어회로
KR890001271U (ko) 메모리 영역 확장 회로

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19961230

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee