KR900004174B1 - Pulse width measuring circuit by controlling micro-process - Google Patents

Abstract

The counters (16,17) are set with certain numbers provided from the data bus through latches (14,15). The flip-flops (18,19) connected to the output of the counters provide outputs (Q1,Q2) as the range of the test input pulse through buffers. The certain number entered to the counters is increased and decreased recursively to find out the optimal value of the pulse width while the test input pulses are entered.

Description

Pulse width measuring device by microprocessor control

1 is a circuit diagram of the present invention.

2 is a flowchart of the present invention.

* Explanation of symbols for main parts of the drawings

10: central processing unit 11: decoder

12: Romans 13: Ram

14,15: latch 16,17: counter

18,19: flip-flop 20: buffer

21: display drive portion 22: display portion

The present invention relates to an apparatus capable of checking the pulse width of a signal input by program control.

Typically, an oscilloscope or logic analyzer is used to check the pulse width of a signal.

However, since the equipment is bulky and expensive, there is no easy way to measure the pulse width when the equipment is not provided.

The present invention has been drawn to solve the above problems, and an object thereof is to provide an apparatus capable of measuring a pulse width, such as an oscilloscope or a logic analyzer.

In order to achieve the above object, the present invention configures a circuit using a microprocessor, a latch, a counter, and a logic element, and measures the signal width of an input pulse under program control of the microprocessor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

)와 대치(14,15)의 로드신호(

)와 버퍼(20)의 출력 인에이블신호(

)로서 인가하고, 상기 각 래치(14,15)와 버퍼(20)는 각각 카운터(16,17)와 플립플롭(18,19)을 통하여 연결된다.1 is a circuit diagram of the present invention, in which a ROM 12 and a RAM 13 are connected to each other via a data bus and an address bus of a central processing unit 10, and the decoder 11 is connected to an address bus of the central processing unit 10. The decoded output is transmitted to the chill select signal of the ROM 12 and the RAM 13.

) And load signals (14, 15)

) And the output enable signal of the buffer 20 (

), And each of the latches 14 and 15 and the buffer 20 are connected via the counters 16 and 17 and the flip-flops 18 and 19, respectively.

)단자와 플립플롭(18,19)의 클리어단자(

)에는 테스트펄스 상승에서 검출 펄스가 반전되어 인가되며, 카운터(16,17)의 클럭단자에는 별도의 클럭펄스가 인가된다.In addition, test pulses are inverted and applied to the load terminals LD of the counters 16 and 17 and the clock terminals of the flip-flops 18 and 19, and the interrupt of the central processing window 10

Terminals and Clear Terminals for Flip-Flops (18, 19)

), The detection pulse is inverted and applied when the test pulse rises, and a separate clock pulse is applied to the clock terminals of the counters 16 and 17.

The operation of the circuit of the present invention having the above configuration will be described below.

Under the control of the central processing unit 10, " 1 " is set in the latch 14 and " FF " If there is no pulse at the test pulse input terminal, the high level signal is applied to the load terminal LD of the counters 16 and 17. Therefore, the values of the counters 16 and 17 are equal to the values of the latches 14 and 15 at the front end. Lose.

)에는 로우레벨신호가 인가되어 출력단자(Q₁, Q₂)신호는 모두 로우레벨이 된다.When the test input pulse becomes high level, the clear terminal of the flip-flop (18, 19) (

) Is applied to the low level signal so that the output terminals Q ₁ and Q ₂ are all at the low level.

At the same time, the low level is input to the load terminals LD of the counters 16 and 17 and the counters 16 and 17 continue to count down by the clock applied at high speed. O ₁ or O ₂ ) becomes the high level.

The CPU 10 waits for the test input pulse to be at the low level, and when the test input pulse is at the low level, the output values of the counters 16 and 17 are applied to the flip-flops 18 and 19 as counted results. do.

In this case, the output signal of the flip-flops 18 and 19 according to the input signal may be represented as follows.

TABLE 1

That is, as shown in (Table 1), if the outputs Q ₁ and Q ₂ are all at the low level, since the pulse is less than the detection limit as the clock, the display unit 22 indicates that the test input pulse is too small. If both (Q ₁ , Q ₂ ) are at the high level, the display unit 22 indicates that the pulse is too large to be detected.

In both cases, that is, when the pulse is too small or too large, the test input pulse can be measured by adjusting the clock pulse input to the counters 16 and 17.

On the other hand, in Table 1, if the output Q ₁ is high level and the output Q ₂ is low level, the value of the test input pulls is between the latch 14 and the latch 15 values. Increasing the value or decreasing the value of the latch 15 and repeating until the difference between the value of the latch 14 and the latch 15 is narrowed to 1, the value of the latch 14 or the latch l5 at that time The value can be calculated within the width of the actual input test input pulse and an error of one clock.

2 is a flow chart of the present invention with reference to this description of the pulse width measurement method of the present invention as follows.

First, before checking the pulse width, when the test pulses for storing and measuring "1" and "FF" are input to the latch 14 and the latch 15, respectively, the buffer 20 value is read.

Then, as the output signal of the flip-flops 18 and 19, the presence range of the pulse width is recognized, and the latch 14 is increased or latched so that the pulse width exists outside the set values of the latch 14 and the latch 15 described above. (15) is reduced and the test pulse is again inputted to check the range of the pulse width so that a test pulse exists between the latch 14 and the latch 15 so that the pulse value is measured and displayed through the display unit. To do that.

An effect of the present invention as described above is that it is possible to provide a convenience that can simply measure the pulse width without using a dedicated device for measuring the pulse width.

Claims (2)

ROM 12 and RAM 13 for storing data, decoder 11 for generating element control signals, display driver 21 and display 22 for visual output of the data, and control of the entire system. In a control system by a microprocessor comprising a central processing unit (10), a constant value is set from the data bus to the counters (16, 17) via the latches (14, 15), respectively, and the counters (16, 17) The outputs of the test input pulses as the output signals Q ₁ and Q ₂ of the flip flops 18 and 19 by operating the counters 16 and 17 during the test input pulses by connecting the outputs of the Pulse width measurement apparatus by a microprocessor control, characterized in that configured to output the range through the buffer. 2. The method of claim 1, wherein the predetermined value inputted to the counters 16 and 17 through the latches 14 and 15 is increased to find the value of the nearest pulse width by repeating the pulse measuring operation during the test input pulse. Pulse width measurement apparatus by a microprocessor control, characterized in that the control.

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