KR890009178A - Full White Balancing Circuit for Video Cameras - Google Patents

Full White Balancing Circuit for Video Cameras Download PDF

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Publication number
KR890009178A
KR890009178A KR1019870012459A KR870012459A KR890009178A KR 890009178 A KR890009178 A KR 890009178A KR 1019870012459 A KR1019870012459 A KR 1019870012459A KR 870012459 A KR870012459 A KR 870012459A KR 890009178 A KR890009178 A KR 890009178A
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KR
South Korea
Prior art keywords
gate
registers
outputs
output
signal
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Application number
KR1019870012459A
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Korean (ko)
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KR900005189B1 (en
Inventor
윤종
윤종경
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삼성전자 주식회사
안시환
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Priority to KR1019870012459A priority Critical patent/KR900005189B1/en
Publication of KR890009178A publication Critical patent/KR890009178A/en
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Publication of KR900005189B1 publication Critical patent/KR900005189B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/40—Circuit details for pick-up tubes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/73—Colour balance circuits, e.g. white balance circuits or colour temperature control

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Color Television Image Signal Generators (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음No content

Description

비디오 카메라에 있어서 풀 화이트 밸런싱 회로Full White Balancing Circuit for Video Cameras

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 회로도.1 is a circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10,20 : 제1,2이득조절회로 12,26~28,15~18 : 앤드게이트10,20: 1st, 2nd gain control circuit 12,26 ~ 28,15 ~ 18: And gate

30,40 : 제1,2검출회로 19 : 오아게이트30,40: 1st, 2nd detection circuit 19: Oagate

50,60 : 제1,2비교기 29,31 : 제1,2스위치회로50,60: first and second comparators 29,31: first and second switch circuits

13,14 : 제1,2카운터 32,33 : 제1,2아나로그/디지탈변환기13,14: 1st, 2nd counter 32,33: 1st, 2nd analog / digital converter

25 : 분주기 21,22 : 제1,2레지스터25: divider 21, 22: 1st, 2nd register

24,23 : 제3,4레지스터 70 : 엔코더24,23: 3rd and 4th register 70: Encoder

Claims (1)

제1,2색차신호 입력단(R-Y,B-Y)으로 입력되는 색차신호의 이득을 조절하는 제1,2이득조절회로(10,20)와, 상기 제1,2이득조절회로(10,20)의 출력을 DC화하여 색차신호의 레벨을 검출하는 제1,2검출회로(30,40)와, 상기 제1,2검출회로(30,40)의 출력과 기준값(Vref)을 비교하는 제1,2비교기(50,60)와, 상기 제1,2이득조절회로(10,20)에 조절된 신호를 3.68MHZ로 변조한 후 다음단의 휘도(Y)신호와 복조되도록 하는 엔코더(70)를 구비한 비디오 카메라의 화이트 밸런스 조정회로에 있어서, 상기 제1,2비교기(50,60)의 출력값에 따라 카운트 업/다운 모드가 설정되어 앤드게이트(12)를 통해 출력되는 수직동기펄스신호를 카운트하는 제1,2카운터(13,14)와, 상기 앤드게이트(12)의 출력 수직동기 펄스신호를 소정 분주하는 분주기(25)와, 상기 제1,2카운터(13,14)의 출력을 저장하는 제1,2레지스터(21,22)와, 상기 제1,2레지스터(21,22)의 출력을 색보정 값으로 저장하는 제3,4레지스터(24,23)와, 상기 분주기(25)의 출력을 앤드하여 상기 제1,2레지스터(21,22)의 로드(Load) 신호를 공급하는 앤드게이트(27)와, 상기 분주기(25)의 출력을 앤드하여 상기 제3,4레지스터(24,23)의 로드신호를 공급하는 앤드게이트(26)와, 상기 앤드게이트(12)와 앤드게이트(26)의 출력을 앤드하여 제3,4레지스터(24,23)의 클럭신호를 공급하는 앤드게이트(28)와, 상기 앤드게이트(12)의 출력과 앤드게이트(27)의 출력을 앤드하여 제1,2레지스터(21,22)의 클럭신호로 공급하는 앤드게이트(34)와, 상기 제1,2카운터(13,14)의 출력을 앤드게이트(15~18)에서 앤드하고 오아게이트(19)에서 논리합하여 인버터(11)를 통해 수직 동기 드라이브 펄스신호의 입력을 제어하는 제어수단(35)과, 상기 제어수단(35)의 제어신호에 따라 제1,2카운터(13,14)와, 제3,4레지스터(24,23)의 출력을 선택하여 출력하는 제1,2스위칭회로(29,31)와, 상기 제1,2스위칭 회로(29,31)의 출력을 아나로그 신호로 변환하여 상기 제1,2이득조절회로(10,20)에 입력되어 W/B를 조절할 수 있도록 하는 제1,2디지탈/아나로그변환기(32,33)로 구성됨을 특징으로 하는 비디오 카메라에 있어서 풀 화이트 밸런싱회로.The first and second gain control circuits 10 and 20 for adjusting gains of the color difference signals inputted to the first and second color difference signal input terminals RY and BY, and the first and second gain control circuits 10 and 20, respectively. First and second detection circuits 30 and 40 for detecting the level of the color difference signal by converting the output into DC, and first and second outputs comparing the outputs of the first and second detection circuits 30 and 40 and the reference value Vref. 2 encoders 50 and 60 and an encoder 70 for modulating the signal adjusted by the first and second gain control circuits 10 and 20 to 3.68 MHZ and then demodulating the luminance (Y) signal of the next stage. In the white balance adjustment circuit of the video camera, a count up / down mode is set according to the output values of the first and second comparators 50 and 60 to count the vertical synchronization pulse signal output through the AND gate 12. The first and second counters 13 and 14, the divider 25 for dividing the output vertical synchronization pulse signal of the AND gate 12, and the outputs of the first and second counters 13 and 14, respectively. First and second registers to store (2 1 and 22, third and fourth registers 24 and 23 for storing the outputs of the first and second registers 21 and 22 as color correction values, and the outputs of the divider 25 and the An AND gate 27 for supplying load signals of the first and second registers 21 and 22 and an output of the divider 25 to load the third and fourth registers 24 and 23. An AND gate 26 for supplying a signal, an AND gate 28 for supplying a clock signal of the third and fourth registers 24 and 23 by AND outputting the AND gate 12 and the AND gate 26. And an AND gate 34 for supplying the output of the AND gate 12 and the output of the AND gate 27 to the clock signals of the first and second registers 21 and 22, and the first and second counters ( Control means (35) for controlling the input of the vertical synchronous drive pulse signal through the inverter (11) by ANDing the outputs of the 13 and 14 at the AND gates 15 to 18 and OR at the OR gate 19; Control system of the means 35 The first and second counters 13 and 14, the first and second switching circuits 29 and 31 for selecting and outputting the outputs of the third and fourth registers 24 and 23, and the first and second switching. First and second digital / analog converters 32 for converting outputs of circuits 29 and 31 into analog signals and inputting the first and second gain control circuits 10 and 20 to adjust W / B. , 33) a full white balancing circuit in a video camera. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870012459A 1987-11-05 1987-11-05 Full white balancing circuit of video camera KR900005189B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870012459A KR900005189B1 (en) 1987-11-05 1987-11-05 Full white balancing circuit of video camera

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870012459A KR900005189B1 (en) 1987-11-05 1987-11-05 Full white balancing circuit of video camera

Publications (2)

Publication Number Publication Date
KR890009178A true KR890009178A (en) 1989-07-13
KR900005189B1 KR900005189B1 (en) 1990-07-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870012459A KR900005189B1 (en) 1987-11-05 1987-11-05 Full white balancing circuit of video camera

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Also Published As

Publication number Publication date
KR900005189B1 (en) 1990-07-20

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