KR890008835Y1 - Circuits for selecting synchronous communication port of computer system - Google Patents

Circuits for selecting synchronous communication port of computer system Download PDF

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Publication number
KR890008835Y1
KR890008835Y1 KR2019860021611U KR860021611U KR890008835Y1 KR 890008835 Y1 KR890008835 Y1 KR 890008835Y1 KR 2019860021611 U KR2019860021611 U KR 2019860021611U KR 860021611 U KR860021611 U KR 860021611U KR 890008835 Y1 KR890008835 Y1 KR 890008835Y1
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output
computer system
communication port
data interface
circuits
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KR2019860021611U
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KR880013099U (en
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정광영
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삼성전자 주식회사
한형수
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Communication Control (AREA)

Abstract

내용 없음.No content.

Description

컴퓨터 시스템의 비동기통신 포트 선택회로Asynchronous Communication Port Selection Circuit of Computer System

첨부된 도면은 본 고안의 회로도.The accompanying drawings are circuit diagrams of the present invention.

*도면의 주요부분에 대한 부호의 설명.* Explanation of symbols for the main parts of the drawings.

G1-G9 : 논리게이트 UART : 비동기데이터인터페이스G1-G9: Logic Gate UART: Asynchronous Data Interface

TB1-TB4 : 3상태버퍼 R1-R7 : 저항TB1-TB4: 3-state buffer R1-R7: Resistance

본 고안은 컴퓨터 시스템의 비동기통신의 포트선택회로에 관한 것이다.The present invention relates to a port selection circuit for asynchronous communication of a computer system.

종래, IBM-PC의 비동기통신에서 두개의 포트(Port)를 이용해서 데이터통신이 이루어지고 있고, 어드레스와 인터럽트신호를 선택하는 포트에 맞게 스위치를 전화시키기 위해서는 두개의 스위치를 이용해야 효과적으로 포트운영을 할수 있었다.Conventionally, data communication is performed using two ports in asynchronous communication of IBM-PC, and two switches must be used to effectively switch ports according to a port for selecting an address and an interrupt signal. Could.

따라서, 본 고안의 목적은 하나의 스위치를 이용해서 복잡한 포트선택을 간단히 처리할수 있도록 하는 회로를 제공하는데 있다.Accordingly, an object of the present invention is to provide a circuit that can simplify the complicated port selection using a single switch.

이하 첨부 도면에 의거하여 본 고안의 실시예를 상세 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부도면에서, 점선부분은 본 고안의 회로도로서, 비동기데이터 인터페이(UART)에서 출력되는 신호(OUT2)는 반전게이트(G1)를 거쳐 낸드게이트(G3,G4)에 인가되고, 스위치(SW)의 절환에 따라 인가되는 신호(S1)는 저항(R2)을 거쳐서 반전게이트(G2)와 낸드게이트(G3)에 인가되며, 반전게이트(G2)에 의해 반전된후 출력되는 신호(S2)는 낸드게이트(G4)에 인가된다.In the accompanying drawings, the dotted line is a circuit diagram of the present invention, and the signal OUT2 output from the asynchronous data interface UART is applied to the NAND gates G3 and G4 via the inversion gate G1, and the switch SW The signal S1 applied according to the switching is applied to the inversion gate G2 and the NAND gate G3 through the resistor R2, and the signal S2 output after being inverted by the inversion gate G2 is a NAND gate. Is applied to (G4).

그리고, 낸드게이트(G3,G4)에서 출력되는 신호는 각각 3상태 버퍼(TB3,TB4)의 인에불단자에 인가되고, 이3상태 버퍼(TB3,TB4)의 입력단에는 비동기데이터 인터페이스(UART)에서 출력되는 드라이브디스에이블신호(DDIS)에 따라 인터럽트신호(INT)가 제어되어서 인가되도록 연결한다.The signals output from the NAND gates G3 and G4 are applied to the enable terminals of the tri-state buffers TB3 and TB4, respectively, and the asynchronous data interface UART is connected to the input terminals of the tri-state buffers TB3 and TB4. The interrupt signal INT is controlled and applied according to the output drive disable signal DDIS.

도면에서, 점선부분 이외의 익스클루시브오아게이트(G7,G8)와 낸드게이스(G9)는 시스템이 병렬버스의 인가신호를 입력하여서 비동기데이터 인터페이스(UART)에 칩선택신호(CS2)를 인가하는 어드레스 디코딩회로이고, 반전케이트(G5,G6)와 3상태버퍼(TB1,TB2)는 비동기데이터 인터페이스(UART)에서 출력되는 드라이브 디스에이블신호(DDIS)에 의해 인터럽트신호(INT)가 본 고안의 3상태버퍼(TB3,TB4)에 인가되도록 하는 회로이다.In the drawing, the exclusive oA gates G7 and G8 and the NAND gay G9 other than the dotted line are provided by the system inputting the authorization signal of the parallel bus to apply the chip select signal CS2 to the asynchronous data interface UART. The inverting gates G5 and G6 and the tri-state buffers TB1 and TB2 are the address decoding circuits, and the interrupt signal INT is generated by the drive disable signal DDIS output from the asynchronous data interface UART. The circuit is applied to the state buffers TB3 and TB4.

상기 저항(R1-R5)는 풀업(Pull-up)저항으로서, 전원 전압(Vcc)이 낸드게이트(G3,G4)와 3상태버퍼(TB3,TB4)에 안정되게 인가되도록 하는 역할을 한다.The resistors R1-R5 are pull-up resistors, and serve to stably apply the power supply voltage Vcc to the NAND gates G3 and G4 and the tri-state buffers TB3 and TB4.

다음은 상기한 구성을 갖는 본 고안의 회로동작을 설명한다.The following describes the circuit operation of the present invention having the above configuration.

도면에서, 스위치(SW)를 오프시키면, 논리 "1"상태의 전원(Vcc)이 저항(R2)을 거쳐서 낸드게이트(G3)에 인가됨과 동시에 반전게이트(G2)에 의해 논리 "0"신호(G3)로 반전되어서 낸드게이트(G4)에 인가된다.In the figure, when the switch SW is turned off, the power supply Vcc in the logic " 1 " state is applied to the NAND gate G3 via the resistor R2 and at the same time the logic " 0 " It is inverted to G3) and applied to the NAND gate G4.

그리고, 비동기데이터인터페이스(UART)에서 출력되는 신호(OUT2)는 논리 "0"상태로서 반전게이트(G1)에 의해 논리 "1"신호로 반전된 다음 낸득이트(G3,G4)에 인가된다.The signal OUT2 output from the asynchronous data interface UART is a logic " 0 " state and is inverted to a logic " 1 " signal by the inversion gate G1 and then applied to the Nantuit G3 and G4.

이때, 낸드게이트(G4)의 출력단에는 논리 "1"신호가 나타나서 3상태버퍼(TB4)를 인에블시키지 못하나, 낸드게이트(G3)의 출력단에는 논리 "0"신호가 나타나서 3상태버퍼(TB3)를 인에블시킨다.At this time, a logic "1" signal appears at the output terminal of the NAND gate G4 to disable the tri-state buffer TB4, but a logic "0" signal appears at the output terminal of the NAND gate G3, causing the tri-state buffer TB3 to appear. Enable).

따라서, 비동기데이터인터퍼에스(UART)에서 출력되는 인터럽트신호는 3상태버퍼(TB3)를 통해서 출력된다.Therefore, the interrupt signal output from the asynchronous data interface UART is output through the tri-state buffer TB3.

즉, 포트(PORT2)가 선택되어서 인터럽트신호가 출력된다.That is, the port PORT2 is selected and the interrupt signal is output.

그러나, 스위치(SW)를 온시키면, 낸드게이트(G3,G4)의 출력단신호는 각각 논리 "0"상태와 논리 "1"상태가 되어서 3상태 버퍼(TB4)만 인에이블시킨다.However, when the switch SW is turned on, the output terminal signals of the NAND gates G3 and G4 are in a logic "0" state and a logic "1" state, respectively, to enable only the three-state buffer TB4.

따라서 인터럽트신호가 3상태버퍼(TB4)를 통하여 포트(PORT1)가 선택되어서 출력된다.Therefore, the interrupt signal is outputted by selecting the port PORT1 through the tri-state buffer TB4.

이상과 같이 본 고안에 의하면 하나의 스위치의 조작에 의해서 포트선택이 간단하게 이루어질 수 있다.According to the present invention as described above, the port selection can be made simply by the operation of one switch.

Claims (1)

반전게이트(G1)를 통한 비동기 데이터 인터페이스(UART)의 출력신호(OUT2)와 스위치(SW)조작에 따라 서로 반전된 각각의 신호(S1,S2)를 함께 낸드게이트(G3,G4)에 입력하고, 상기 낸드게이트(G3,G4)의 각 출력신호에 의해서 선택되어 인에이블되는 3상태버퍼(TB3,TB4)를 통해서 비동기 데이터 인터페이스(UART)에서 출력되는 인터럽트신호(INT)가 출력되도록 연결한 것을 특징으로 하는 컴퓨터 시스템의 비동기 통신 포트선택회로.The output signal OUT2 of the asynchronous data interface UART through the inversion gate G1 and the signals S1 and S2 inverted from each other according to the operation of the switch SW are input together to the NAND gates G3 and G4. And connected to output an interrupt signal INT output from the asynchronous data interface UART through the three-state buffers TB3 and TB4 selected and enabled by the respective output signals of the NAND gates G3 and G4. Asynchronous communication port selection circuit of a computer system characterized in that.
KR2019860021611U 1986-12-29 1986-12-29 Circuits for selecting synchronous communication port of computer system KR890008835Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019860021611U KR890008835Y1 (en) 1986-12-29 1986-12-29 Circuits for selecting synchronous communication port of computer system

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KR2019860021611U KR890008835Y1 (en) 1986-12-29 1986-12-29 Circuits for selecting synchronous communication port of computer system

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KR890008835Y1 true KR890008835Y1 (en) 1989-12-05

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