KR890005750Y1 - Synchronizing level circuit - Google Patents

Synchronizing level circuit Download PDF

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Publication number
KR890005750Y1
KR890005750Y1 KR2019860009188U KR860009188U KR890005750Y1 KR 890005750 Y1 KR890005750 Y1 KR 890005750Y1 KR 2019860009188 U KR2019860009188 U KR 2019860009188U KR 860009188 U KR860009188 U KR 860009188U KR 890005750 Y1 KR890005750 Y1 KR 890005750Y1
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South Korea
Prior art keywords
transistor
signal
synchronization
delay element
output
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KR2019860009188U
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Korean (ko)
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KR880001496U (en
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한홍수
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삼성전자주식회사
한형수
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Priority to KR2019860009188U priority Critical patent/KR890005750Y1/en
Publication of KR880001496U publication Critical patent/KR880001496U/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/05—Synchronising circuits with arrangements for extending range of synchronisation, e.g. by using switching between several time constants
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Picture Signal Circuits (AREA)

Abstract

내용 없음.No content.

Description

동기레벨 보정회로Sync level correction circuit

본 고안의 회로도.Circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 지연소자 2 : 동기분리부1: delay element 2: synchronization separator

3 : 비교부 4 : 증폭부3: comparison unit 4: amplification unit

5 : 감쇄부 Q1, Q2, Q3: 트랜지스터5: Attenuation part Q 1 , Q 2 , Q 3 : Transistor

CP1:비교기 C1, C2, C3: 콘덴서CP 1 : comparator C 1 , C 2 , C 3 : condenser

R1, R2, R3, : 저항 T : 트랩R 1 , R 2 , R 3 ,: Resistance T: Trap

본 고안의 복합 영상 신호에서 휘도 신호로 분리되는 동안에 동기 신호가 변하는 것을 방지하기 위한 동기 레벨 보정회로에 관한 것이다.A synchronization level correction circuit for preventing a synchronization signal from changing while being separated into a luminance signal in a composite video signal of the present invention.

종래에는 별도로 동기 레벨 보정기 회로를 구성시키지 않기 때문에 복합 영상 신호의 레벨 변동에 따라 동기 신호가 불완전하여지는 원인이 되어 화질이 떨어지는 단점이 있는 것이다.In the related art, since the synchronization level corrector circuit is not separately configured, the synchronization signal is incomplete due to the level variation of the composite video signal, and thus the image quality is deteriorated.

본 고안은 이와 같은 점을 감안하여 복합 영상 신호의 레벨 변동에 따른 동기 신호와 설정된 기존 레벨과 비교하여 동기신호의 레벨을 보정할 수 있게 한 것으로, 이를 첨부 도면에 의하여 상세히 설명하면 다음과 같다.The present invention allows the level of the synchronization signal to be corrected by comparing the synchronization signal according to the level variation of the composite video signal with the existing level, which will be described in detail with reference to the accompanying drawings.

복합영상 신호(VIP)가 트랜지스터(Q1)(Q2) 및 저항(R1- R6)으로 구성된 증폭부를 통하여 트랩(T)에서 일측으로 지연소자(1)에 인가되게 구성시켜 저항(R9)(R10) 및 콘덴서(C1)를 통하여 휘도신호(Y신호)가 출력되게 구성하고, 지연소자(1)의 전단에서 트랜지스터(Q4)로 구성된 동기 분리부(2)의 출력이 저항(R11)(R12)으로 분배되어 비교부(CP1)의 일측단자(+)에 긴가되게 구성시키며 타측 단자(-)에는 저항(R14)을 통하여 기준 전압이 인가되게 비교부(3)를 구성시킨 후 트랜지터(Q1)의 베이스축과 연결된 증폭부(4) 및 감쇄부(5)를 제어하게 구성시킨 것으로, 다이오드(D2)를 통하여 애미터측이 가변 저항(VR1)과 연결된 PNP 트랜지스터(Q6)의 베이스축을 연결구성하여 증폭부(4)를 구성한 다이오드(D1)를 통하여 트랜지스터(Q5)의 베이스축과 연결되게 감쇄부(5)를 구성시켜 된 것이다.The composite image signal VIP is configured to be applied to the delay element 1 to one side of the trap T through an amplifying unit composed of transistors Q 1 and Q 2 and resistors R 1 to R 6 , thereby providing a resistance R. 9 ) The luminance signal (Y signal) is output through the R 10 and the condenser C 1 , and the output of the synchronous separator 2 composed of the transistor Q 4 at the front end of the delay element 1 The resistors R 11 and R 12 are distributed to one terminal (+) of the comparator CP 1 , and the other terminal (-) is applied with a reference voltage through the resistor R 14 . 3) is configured to control the amplifier 4 and the attenuator 5 connected to the base axis of the transistor (Q 1 ), the emitter side through the diode (D 2 ) the variable resistor (VR) 1 ) is connected to the base axis of the PNP transistor (Q 6 ) connected to the attenuation to be connected to the base axis of the transistor (Q 5 ) through the diode (D 1 ) constituting the amplifier (4) The part 5 was comprised.

이와 같이 구성된 본 고안에서 복합 영상신호(VIP)가 트랜지스터(Q1)의 베이스측에 인가되어 증폭된 신호가 트랜지스터(Q1)의 콜렉터측에 베이스축이 연결된 트랜지스터(Q2)로 증폭된 후 저항(R7)과 트랩(T)을 통하여 진폭 분리된 휘도 신호(Y신호)가 지연소자(1)를 통하여 일정시간 지연된 후 직류 차단용 콘덴서(C1)를 통하여 출력하게 된다.Thus, after the amplification to the composite video signal (VIP) and the transistor (Q 1) of the transistor (Q 2) the base shaft is connected to the collector side of the amplified signal is applied to the base side of the transistor (Q 1) in the present design is configured The luminance signal (Y signal) amplitude separated through the resistor (R 7 ) and the trap (T) is delayed for a predetermined time through the delay element (1) and then output through the DC blocking capacitor (C 1 ).

이때에 지연소자(1)의 전단에서 동기분리부(2)로 인가되는 수직 동기 신호가 콘덴서(C2)를 통하여 트랜지스터(Q4)를 구동시키게 되는 것으로, 저항(R11)(R12)으로 분배된 동기 신호가 비교기(CP1)의 일측단자(+)에 인가되고, 저항(R14)을 통하여 기 설정된 전압(300mv)이 타측단자(-)에 인가되어 기준 전압보다 높을때에는 비교기(CP1)의 고전위 상태로 신호가 다이오드(D1)를 통하여 트랜지스터(Q5)의 베이스측에 인가하게 되며, 기준 전압 보다 낮을때에는 비교기(CP1)의 저 전위 상태 신호가 다이오드(D2)를 통하여 PVR트랜지스터 (Q6)의 베이스측에 인가하게 된다.At this time, the vertical synchronizing signal applied to the synchronizing separator 2 at the front of the delay element 1 drives the transistor Q 4 through the capacitor C 2 , and thus the resistor R 11 (R 12 ). When the synchronization signal divided by is applied to one terminal (+) of the comparator CP 1 , and the preset voltage 300mv is applied to the other terminal (−) through the resistor R 14 , the comparator ( when the signal to the high-potential state of CP 1) and that applied to the base side of through the diode (D 1) the transistor (Q 5), lower than the reference voltage is a low potential state signal of the comparator (CP 1) diodes (D 2 ) Is applied to the base side of the PVR transistor Q 6 .

즉, 비교기(CP1)에서 설정된 기준 전압과 휘도신호 출력의 동기 레벨을 비교하여 증폭부(4) 및 감쇄부(5)를 제어하는 것으로, 감쇄부(5)의 트랜지스터(Q5)가 도통할때에는 트랜지스터(Q1)의 베이스축에 인가되는 복합 영상신호가 트랜지스터(Q5)로 흐르게 되어 동기 레벨을 안정시키게 되고, 증푹부(6)의 트랜지스터(Q6)가 도통할때에는 트랜지스터(Q6)의 출력이 복합영상 신호(VIP)에 합성되므로 트랜지스터(Q1)에 베이스축에 중가된 신호가 인가되어 동기 레벨을 항상 일정하게 유지시킬수 가 있는 것이다.That is, the transistor Q 5 of the attenuator 5 is turned on by controlling the amplifier 4 and the attenuator 5 by comparing the reference voltage set by the comparator CP 1 with the synchronization level of the luminance signal output. In this case, the composite video signal applied to the base axis of the transistor Q 1 flows to the transistor Q 5 to stabilize the synchronization level. When the transistor Q 6 of the recessed portion 6 conducts, the transistor Q Since the output of 6 ) is combined with the composite video signal VIP, the signal weighted to the base axis is applied to the transistor Q 1 so that the synchronization level can be kept constant at all times.

이상에서와 같이 본 고안은 복합 영상신호의 레벨 변동에 따라 동기가 불안정 되는 것을 검출하여 비교부의 설정된 기준 전압과 비교하여 영상신호의 레벨을 일정하게 유지시킬수 있어 비데오 회로의 화질을 개선시킬 수 있는 이점이 있는 것이다.As described above, the present invention detects that the synchronization is unstable due to the level variation of the composite video signal, and maintains the level of the video signal constant compared with the set reference voltage of the comparator, thereby improving the image quality of the video circuit. Is there.

Claims (1)

복합영상 신호(VIP)가 증폭용 트랜지스터(Q1)(Q2)와 트랩(T)을 통하여 지연소자(1)에 인가된 후 휘도신호(Y)를 검출시키는 회로에 있어서, 트랜지스터(Q1)의 베이스측과 지연소자(1)의 전단에 동기 분리부(2)의 출력과 비교부(3)의 기준 레벨이 비교되게 구성시킨 후 후단에 연결된 증폭부(4) 및 감쇄부(5)의 출력이 제어되게 구성한 동기 레벨 보정회로.In the circuit for detecting the luminance signal (Y) after the composite video signal (VIP) is applied to the delay element (1) through the amplifying transistor (Q 1 ) (Q 2 ) and the trap (T), the transistor (Q 1) Amplification section 4 and attenuation section 5 connected to the rear stage after the output of the synchronous separation section 2 and the reference level of the comparison section 3 are configured to be compared at the base side of the base and the front end of the delay element 1. A synchronization level correction circuit configured to control the output of the signal.
KR2019860009188U 1986-06-27 1986-06-27 Synchronizing level circuit KR890005750Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019860009188U KR890005750Y1 (en) 1986-06-27 1986-06-27 Synchronizing level circuit

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Application Number Priority Date Filing Date Title
KR2019860009188U KR890005750Y1 (en) 1986-06-27 1986-06-27 Synchronizing level circuit

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KR880001496U KR880001496U (en) 1988-03-15
KR890005750Y1 true KR890005750Y1 (en) 1989-08-26

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