KR890004851B1 - Charactor generator controller of double scan - Google Patents

Abstract

The controller includes a dividing means (20) for dividing horizonal synchronous signal to two different signals, first and second synchronous signals having the same period as data for chractor generating, delaying units (30,40) for delaying first and second signals, a gate (50) for adding horizontal synchronous delaying signals logically and transmitting as a double scan horizontal syncronous signal, and a charactor generator (60) having charactor generating chip for generating charator data with the same period as that of double scaner.

Description

Character Generator Control Circuit of Double Scan Television

1 is a block diagram of the present invention.

2 is a concrete circuit diagram of one embodiment of the block diagram of FIG.

3 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: microcomputer 20: horizontal synchronization signal division

30, 40: first and second horizontal synchronization signal delay unit 50: horizontal synchronization signal output gate

60: character generator circuit 70: output logic circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character generator controller of a double scan television, in particular a double scan television of a non-interlace method using an interlace molecular generation chip. It is a control circuit of a double scan television that allows a character to be generated.

In general, a character generation circuit of a television is intended to display a number or a letter indicating a time or a channel on a screen of a television receiver in a predetermined area, and a dedicated integrated circuit for this has been developed and used.

However, the above-mentioned character generation chip can be used only for character generation of conventional (general purpose) television sets. Recently, there has been a trend for the emergence of non-interlaced double scan televisions, but the character generation chips for non-interlaced double scan televisions have not been developed. It is not.

If the above character generation chip is used for character generation of double scan television, the horizontal scan frequency of general television is 15.743KHz or the horizontal scan frequency of double scan television receiver is about 2H about 31.5KHz. It was impossible to use.

Therefore, in the non-interlaced double scan television receiver, it was not possible to display characters on the screen of the television set using a general-purpose character generation chip.

Accordingly, an object of the present invention is to provide a character generation control circuit capable of generating characters in a double scan television of a non-interlaced system using a plurality of general-purpose character generation chips.

It is still another object of the present invention to provide a circuit capable of realizing a high quality screen without flicker noise at the time of character generation. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a character generation control circuit of an interlaced double scan television according to the present invention, and includes a microcomputer unit 10 for processing and outputting data corresponding to a character to be displayed on a screen of a television receiver according to a program; And a horizontal synchronous signal division unit 20 for latching the first and second horizontal synchronous signals mutually opposite to each other in a cycle of character generation data by inputting a double scan horizontal synchronous signal of a non-interlaced double scan television receiver as a clock. A first horizontal synchronizing signal delay unit 30 delaying the first horizontal synchronizing signal output from the synchronizing signal dividing unit 20 and delay detecting the delay synchronizing signal and the first horizontal synchronizing signal; A second horizontal synchronizing signal delay unit 40 delaying the second horizontal synchronizing signal output from the installment unit 20, and delay detecting the delay synchronizing signal and the second horizontal synchronizing signal; A horizontal synchronizing signal output gate 50 for outputting the horizontal synchronizing signal of the double scan television to each circuit unit by logically combining the first and second delay synchronizing signals output from the first and second horizontal synchronizing signal delay units 30-40, Characters that generate a character generation signal by driving a character generation chip composed of a plurality of program data output from the microcomputer 10 and horizontal synchronization signals respectively output from the first and second vertical synchronization signal delay units 30-40. It consists of a generation circuit section 60 and an output logic circuit 70 for logically combining and outputting the character generation signal of the character generation circuit section 60.

Therefore, the program data and control signal for character generation at the microcomputer part in the non-interlaced double scan receiver are output to the character generating circuit part 60, and the horizontal synchronous signal at the deflection part of the receiver set (hereinafter referred to as HS). ) And a vertical synchronizing signal (hereinafter referred to as VS) are generated and input to the horizontal synchronizing signal dividing unit 20 and the character generating circuit unit 60, respectively, and the horizontal synchronizing signal dividing unit 20 is the horizontal synchronizing signal. When the clock is a falling edge, the signal is input to the clock and the latch is divided into a first horizontal synchronizing signal and a second horizontal synchronizing signal, which is an inverted signal, to divide the first horizontal synchronizing signal delay unit 30 and the first horizontal synchronizing signal. Outputs to the two horizontal synchronization signal delay units 40, respectively.

At this time, the first horizontal synchronizing signal delay unit 30 inputting the first horizontal synchronizing signal output from the horizontal synchronizing signal splitting unit 20 delays it for a predetermined time and synchronizes it with the input first horizontal synchronizing signal. The second horizontal synchronous signal delay unit 40 outputs the delayed first horizontal synchronous signal to the horizontal synchronous signal output gate 50 and the character generating circuit unit 60, and inputs the second horizontal synchronous signal to the second horizontal synchronous signal. Delays the signal for a predetermined time and synchronizes it with the input horizontal synchronous signal and outputs it to the horizontal synchronous signal output gate 50 and the character generating circuit 60.

Therefore, the synchronization signal output gate 50 sequentially outputs the first and second horizontal synchronization signals sequentially generated by ORing the first horizontal synchronization signal and the second horizontal synchronization signal, thereby requiring the horizontal synchronization signal of the double scan television receiver. The furnace is supplied to each circuit.

In addition, the data and the control signal for the character generation output from the microcomputer 10 and the vertical synchronization signal generated in the deflection unit of the double scan television receiver and the first and second horizontal synchronization signal delay unit (30-40) respectively output The character generating circuit unit 60 inputs the first and second horizontal synchronization signals to be outputted to the output logic circuit 70 at a high speed by the first and second horizontal synchronization signals which are separately input. do.

On the other hand, the output logic circuit 70 inputs the character generation data output from the character generation circuit unit 60, and outputs a screen (Screen: Cathode ray tude) roll that matches the speed of the horizontal synchronization frequency of the double scan television. do.

Therefore, the horizontal scan frequency of the double scan television, which is twice as fast as the horizontal scan of the general-purpose television, is divided into the first and second horizontal synchronizing units, and the delay is converted into the general vertical synchronization frequency to generate the characters of the non-interlaced double scan television. You can.

FIG. 2 is a specific circuit diagram of an embodiment of the block diagram of FIG. 1, which includes a microcomputer for outputting character data and control signals to be displayed on a screen of a television receiver according to a predetermined program, and a power supply voltage ( V _DD ) is inputted to the data input terminal (T) to input the horizontal synchronization signal (31.5KHz) (HS) of the double scan television receiver of the nin interlaced type as a clock, and the state is achieved whenever the clock edge becomes the falling edge. A horizontal synchronous signal divider 20 formed of a T-flip flop (Toggle F / F) for shifting the signal to generate a horizontal synchronous signal at a character generation period, and latching the first and second horizontal synchronous signals. An RC delay circuit in which a capacitor C1 and a resistor R1 are connected in series is connected to an output terminal of an inverter N1 that inverts and outputs the first horizontal synchronization signal outputted from 20, and inverted with the first horizontal synchronization signal. Input the first delayed horizontal synchronization signal And a second horizontal synchronous signal as an inverted output of the first horizontal synchronous signal delay unit 30 and the horizontal synchronous signal splitter 20. The RC delay circuit in which the capacitor C2 and the resistor R2 are connected in series is connected to an output terminal of the inverter N2 which inverts the output of the inverter N2, thereby inverting the inverted second horizontal synchronization signal, and delaying the predetermined second horizontal synchronization signal. A horizontal horizontal signal delay unit 40 comprising an AND gate (AN2) for inputting and outputting an AND, and an OR gate (OR Gate) for logically combining and outputting the outputs of the AND gates (AN1-AN2). Characters are generated by inputting the synchronization signal output gate 50, the outputs of the AND gates AN1-AN2, the vertical synchronization signal VS of the double scan television receiver, and the data and control signals output from the microcomputer described above. Output character generation chip (61-62) By a logical OR character generating data which are respectively outputted from the composed character generator 60, and the character generation chip (61-62) consists of the output logic circuit 70 is a second operation waveform degrees third turn.

, STB) 신호가 각각 출력되어 문자발생칩(61-62)의 데이터 제어신호 입력단자(DCI1)과 (DCI2)로되고, 더블스켄 텔레비죤의 편향부에서 출력되는 수직주파수(VS)가 수직주파수 입력단자(VS1-VS2)로 각각 입력되는 상태에서 제3(a)도와 같은 수평동기 주파수(31.5KHz)(HS)가 수평동기신호 분할수단(20)의 클럭단(CK)으로 입력되면, 수평동기신호 분할수단(20)은 31.5KHz의 주파수로 입력된 인터레스방식의 더블스켄 텔레비죤의 수평동기(HS)가 하강에지로될 때 출력단자(Q-

)에서는 제3(b)도와 제3(c)도와같이 서로 상반된 신호를 2분주하여 출력단자(Q)의 신호를 인버터(N1)과 앤드 게이트(AN1)로 입력시키며, 출력단자(

)의 신호를 인버터(N2)와 앤드 게이트(AN2)로 출력한다.Hereinafter, the present invention will be described with reference to the above-described configuration and drawings. Now, the data (Data) and the control signal (CLK,

, STB) signals are output to the data control signal input terminals (DCI1) and (DCI2) of the character generator chips 61-62, and the vertical frequency (VS) output from the deflection portion of the double scan television is inputted vertical frequency. When the horizontal synchronizing frequency (31.5 KHz) HS as the third (a) is input to the clock terminal CK of the horizontal synchronizing signal dividing means 20 in the state inputted to the terminals VS1-VS2, respectively, the horizontal synchronizing is performed. The signal dividing means 20 outputs the output terminal Q- when the horizontal synchronization HS of the interscan type double scan television input at a frequency of 31.5 KHz becomes the falling edge.

) Divides the signals opposite to each other as shown in the third (b) and the third (c) and inputs the signal of the output terminal Q to the inverter N1 and the AND gate AN1, and output terminal (

) Is output to the inverter N2 and the AND gate AN2.

In addition, the inverter N1 inputs the signal of FIG. 3 (b), inverts the signal of (B) as shown in FIG. 3 (d), and converts it to the capacitor C1 and the resistor R1 to the third (f). As shown in the figure, a predetermined delay is input to the AND gate AN1.

In this case, the AND gate AN1 inputting the first horizontal synchronization signal as shown in FIG. 3 (b) and the first horizontal synchronization signal as shown in FIG. 3 (f) is logically multiplied to obtain the first horizontal synchronization signal as shown in FIG. Only the horizontal synchronous signal is output at 15.75 KHz to the horizontal synchronous signal input terminal HS of the character generator chip 61.

In addition, the inverter N2 which inputs the signal of FIG. 3 (c) inverts this signal and inverts it as shown in FIG. 3 (e), and outputs it to an RC delay circuit composed of capacitor C2 and low sulfur R2, A signal similar to the diagram (g) is output to the AND gate AN2.

Therefore, the AND gate AN2 performs a logical multiplication on the signals of the third (c) and the third (g) degrees, and the horizontal synchronous signal of the character generation chip 62 generates the second horizontal synchronous signal as shown in the third (i) at a period of 15.75 KHz. Output to the input terminal HS2.

Therefore, the molecular generation chip 61-62 outputs the program data output to generate characters from the microcomputer 10 and the horizontal synchronization signal output from the AND gates AN1-AN2 and the vertical synchronization output from the deflection portion of the double scan television. By inputting the vertical synchronization signal input terminal V5 at the frequency (60 Hz), the character generation chips 61-62 alternately output character generation data to the output logic circuit 70 every 15.75 KHz.

In this case, the character generation data sequentially output from the character generation chips 61-62 are logically multiplied and output to the screen of the double scan television through the terminal 200, and the horizontal synchronous signal output gate 50 is the AND gate ( Original horizontal output from the deflection section of the double scan television by combining the first and second horizontal synchronization signals output at 15.75 KHz as shown in the third (h) and the third (i) in AN1) and (AN2) Scanning speed (31.5KHz) is output to each circuit requiring horizontal sync signal.

Therefore, out of the horizontal synchronization frequency of 525 double synchronous double scan televisions, 263 character generation chips 61 and 262 vertical synchronization pulses output character generation data using 262 vertical synchronization pulses. Able to know.

As described above, the present invention constitutes a plurality of interlaced character generation chips, divides and outputs the horizontal synchronization frequency of the double scan skeleton, and generates a character with a conventional horizontal synchronization signal after a predetermined delay time. The horizontal sync signal of the double scan television and the character generation are output in accordance with the horizontal sync signal of the television of the double scan of the non-interlaced method. Therefore, there is an advantage that the general character generation chip can be used in the non-interlaced double scan method.

Claims (1)

In the character generation control circuit of a double scan television having a microcomputer 10 for processing data and control signals according to characters to be displayed on a screen of a television receiver according to a program, the horizontal synchronization frequency of the double scan television of an interlaced method. And a horizontal synchronous signal dividing means (10) for latching and outputting the first and second horizontal synchronous signals which are mutually opposite to each other in a cycle of character generation data, and delaying the first horizontal synchronous output from the means (10). A first horizontal synchronizing delay unit 30 for delay detecting the first horizontal synchronizing signal by synchronizing the delay synchronizing signal with the first horizontal synchronizing signal, and delaying and outputting a second horizontal synchronizing signal outputted from the means 20 A second horizontal synchronization signal delay unit 40 for detecting delay in synchronization with two horizontal synchronization signals, and first and second horizontal synchronization delay signals output from the first and second horizontal synchronization signal delay units 30-40, respectively. Paddy field In addition, the horizontal synchronous signal output gate 50 outputting the original double scan horizontal synchronous signal, and the data and control signals output from the microcomputer 10 and the first and second horizontal synchronous signal delay units 30-40, respectively. Character generation circuit unit 60 for forming a character generation chip composed of a plurality of horizontal synchronization signals to be output and outputting the character generation data in accordance with the double scan period, and logically combining the character generation signal of the character generation circuit unit 60 Circuit characterized in that composed of an output logic circuit 70 to output.

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