SU824281A1 - Device for displaying information on crt screen - Google Patents

Description

 DEVICE FOR DISPLAYING INFORMATION ON CRT SCREEN

the house of the fourth element I, and the output of the first element SH, the fifth shift register, the outputs of which are connected to the first inputs of the switch, and two delay elements, the output of the pulse generator. —connected to the first and fifth inputs of the first, fifth and sixth elements directly, and through the first and second delay elements with the control inputs of the third and fourth fourth shift registers, the inputs of the second OR element are connected to the outputs of the fourth, fifth and seventh AND elements, the outputs of the first and fourth bits of the first shift register through the deflecting voltage driver on the x coordinate is connected to the second inputs of the switch directly and through the inverter, the third switch inputs are connected directly and through the second inverter to the voltage generator on the coordinate y, the inputs of which are connected to the outputs of the third and fourth elements OR, the first the input of the third element OR is connected to the output of the first bit of the second shift register, and the second input is connected to the second input of the fourth element AND, the output of the fifth bit — the second shift register a, the outputs of the second and third bits of which are connected to the inputs of the fourth element OR, and the output of the fourth discharge with the first inputs of the second and third elements And, the output of the second discharge of the third shift register is connected to the second input of the sixth element And, the third input of which is connected to the output of the eighth element And, and the output to the first input of the seventh element And and the second input of the third element And, the outputs of the third bits of the first and third shift registers are connected to the second inputs of the seventh and fifth elements And, respectively, and the high bit of the fourth shift register. ha is connected to the second input of the first element I, the second input of the second element I is connected to the output of the fifth element I, and the third inputs of the second and third elements I are connected to the output of the ninth element I, the input of the fifth shift register is connected to the first input of the tenth element And the output of the fourth element I, and the most significant bit of the second shift register is connected to the second input of the tenth element And, the register outputs are connected to the inputs of the eighth and ninth elements AND,

FIG. 1 shows the functional diagram of the device for displaying and 1 formation; in fig. 2 - a set of micropigrams and timing diagrams of deviating functions; in fig. 3 and 4 principle of displaying information.

The device contains a generator of 1 pulses, the third 2 and fourth 3 shift registers, the first 4 and second shift registers, the fifth shift register 6, the formers 7 and 8 of the bias voltage, the register 9, the switch, 10, elements 11-20, and inverters

21 and 22, elements 23-26 OR, delay elements 27 and 28, start bus 29, bus 30 Symbol code, output buses .3 and 32 (deflection functions in X and UK coordinates 34 Electron beam illumination code, bus 33 End of display ..,

Symbols are formed from 4 trapezoidal 3-connected micropolygram figures (Fig. 2). All figures are identical in shape, but are oriented in different directions. This ensures the formation and display of the entire alphanumeric alphabet with a minimum of hardware costs, shortens the time of image formation, and improves the quality of the displayed characters.

Each micro-polygram consists of five elements (segments), so the shift registers 4 and 5 have five outputs. The pulses at the outputs of shift registers 4 and 5 appear; in sequence, starting from the first output. In turn, each micropigram element is divided into three parts. This division is caused by the fact that the third part of the third, the first and the third part of the even, true, first part of the fifth elements may not be formed depending on the character code entered in register 9. The division of the elements of the micropigram into three equal parts is carried out by the third 2 and the fourth 3 shift registers. In the absence of a control signal, they work as ordinary pulse distributors and signals at its outputs appear

. consistently, starting with the first. But with the arrival of the signal, the control inputs, (shift registers 2 and 3, are transferred to the states corresponding to the presence of potential at eio first regardless of what state it was before the arrival of the signal. The control signal comes from the output of element 23 OR for the third 2 and from the output of element 24 OR for the fourth 3 shift registers / Shifters of the deflection functions 7 and 8 form the analog signals from sequences of pulses coming from the first 4 and second 5 shift registers. The first output of the register. 4 shift is connected to su I am scaling down and the fourth output is with the subtracting input of the ram 7. The first and fifth outputs of the shift register 5 are connected via element 25 OR with the summing input, and the third output is through element 26 OR with the BI reading input of the imager 8. In addition, the third the output of the 4shift register is connected to one input of element 12 I, the fourth output of the register 5 shift is connected to one input of elements 15-i6 AND, and the fifth output with one INPUT of element 17 AND, which 25 together with the element 20 AND 5th of the shift penicrpoM in the form of a bath. End of display. Shift register 6 Together with switch 10, commute the signals received from the output terminals of capacitors 7 and .8 directly and through inverters 21 and 22 and form output signals for buses that are currently being generated by the inverter 21 and 22 (figure 2) The x and y coordinates. Element-27 and 28 delays provide impulse delays that arrive at the inputs of shift registers 2 and 3 by reference to the pulses supplied to the inputs of elements I and 14 and by the value of the pulse duration. Elements I-19 and provide control over the operation of the device in three modes. The first mode of operation is carried out in the absence of signals at the outputs of elements 19 and 18 I. The second mode is characterized by the presence of signals, first at the output of element 18I, and then at the output of element 19I. In the third mode, the signals simultaneously at the outputs of the elements 18 and 19 I. The device operates as follows. At the beginning of the work, the installer serves. pulse, in which all elements of the device are set to the initial state (not shown in Fig. I). At the same time, shift registers 4 and 5, register 9, Shapers 7 and 8 are set to the O state (their outputs have a low voltage level). Registers 2, 3 and 6 shift have signals at the first outputs. On bus 30 (symbol code), a twenty-bit symbol code is written to 2-21 bits of register 9. On the start signal (bus 29), the first and second shift registers are switched to one state (the potential appears at the first outputs of registers 4 and 5) and the generator of 1 pulses is started, from the output of which the pulses arrive at the inputs of elements 11 and 14 AND and through the elements 27 and 28 of the delay to the inputs of the shift registers 2 and 3. At their outputs, the voltage gain corresponding to 1 is consistently distributed. The order of forcing the opoly gram is chosen so that the difference in the process of its formation is observed, starting with the third element. Therefore, the difference in the operation of the device is observed starting from the third state of the shift registers 4 and 5, and depends on the signals on the inputs of elements 18 and 19 AND, ...,. . -; ; Let us consider the operation of the device in all cases on the example of the formation of an oh; micropig in “1 on the first cycle of operation of the registers 4 and 5 of the shift. In the absence of signals at the output: x elements 18 and 19 And (the first mode of operation) the signals at the inputs of the registers 4 and 5 of the shift and come evenly from the outputs; elements 23 and 24 of the NL and all elements of the micro polygram are formed over equal periods of time (Fig. 2). The transfer of the first 4 and second 5 shift registers from one steady state to the Other is carried out at the end of the cycle of the shift registers 2 and 3. At the same time, control signals come from the outputs of elements 11 and 14 I. These signals are formed and fed through the circuit: the third outputs of registers 2 and 3 of the shift, pulses, and those available from the pulse generator, elements 11 and 14 AND, elements 23 and 24 OR, INPUTS The first 4 and second 5 shift registers. . In the case of the presence of a signal, first, and the output of the element 18 And

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The output of the element 19 And (second mode of operation) transfer of the register 4 shift from the retired state to the fourth and transfer of the register 5 shift from the fourth one to the fifth takes place more than usual. This is explained by the fact that the signal from the output of element 18 also arrives at the input of element 13 I. At the same time, the transfer signal from one state to another of shift register 4 is fogcho through the circuit: elements 13 and 12 AND, element .23 OR. Formation of the control signal is possible due to the presence of signals at the second output of shift register 2, third output 15, shift register 4, output of element 18A and the pulse from generator 1. At the same time, the signal from the output of element 23 OR affects the control input register 2 shift 20 and translates it into the first state (the presence of potential at the first output). At this time, the 3 shift register operates on a full cycle and the shift of the 5 shift register to the fourth state is performed by a signal from the output of element 14 I. This happens one clock later than the shift of the 4 shift register to the fourth state.

The transition of the shift register 4 from one state to another is accompanied by the synchronous overwriting of the higher bits to the lowest bits. Therefore, the transition of the shift register 4 from the third state to the fourth is accompanied by the appearance of a 35 signal at the output of element 19I. Since in this case there are no signals at the output of element 18 I and the third output of the shift register 4, the shift of the shift register 4 from the fourth This does not happen through the full cycle of the shift register 2 (in three cycles of the generator of 1 pulses). : The shift of the 5 shift register from the fourth state to the fifth occurs 45 times earlier than usual by 1 clock cycle. This is possible due to the presence of signals simultaneously on the fourth output of the shift register 5 and the outputs of elements 19 and AND I. As a result, element 15 runs. And a signal appears through element 24 OR to the input of the shift register 5 and converts it to fifth state. So the transition of the first 4

and the second 5 shift registers from the fourth state in the fifth and the end of the cycle of their work is one 18

temporarily. The cycle time of their operation is reduced by one cycle.

In the third mode of operation, the signals are first on both outputs of elements 18 and 19 AND, and then on the output of element 19 I. In this case, the first shift register works the same as in the previous mode., Except that in the fifth state it There are only 2 cycles of operation of the generator of 1 pulses. From the fifth state, it is transferred to the initial (first) state by a signal from the output of element 17 AND through element 23 OR. The difference in the operation of the shift register 5 from the previous mode is that in the fourth state it is only one clock cycle. In this case, the shift signal of the shift register 5 from the fourth state to the fifth comes from the output of element 16 AND through element 24 OR. This signal is generated and passes through the circuit: the output of element 18 AND, the second output of shift register 2, the output of element 13 AND, the fourth output of shift register 5, the outputs of element 16 AND 24, OR, the input of shift register 5. In the fifth state of the shift register 5, the time is equal to the register operation cycle. 3 shifts. The cycle time of the device in the third mode of forming a micro-polygram is reduced by two cycles and ends in 13 t,

During operation of the 4 and 5 shift registers, the signals from their outputs (the first and fourth outputs of the shift registers 4, all outputs of the shift register 5, except for the fourth) arrive at the inputs of drivers 7 and 8, the outputs of which form analog signals at the inputs of the switch ten.

Each character is formed in four cycles of operation of registers 4 and 5 shift. At the same time, their operation mode on each cycle may be different and depends on the particular character being formed and displayed.

At the end of the first cycle of the shift register 5, the signal from its fifth output passes through element 17 I and sets the shift register 6 to the second state (a signal appears at the second output).

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Claims (2)

The switch 10, which is controlled by this signal, switches the input signals A, A, B, E into the deflection functions required for the second micro-polygram along the X and Y coordinates (Fig. 2). This process is repeated until the end of the formation of the fourth micro-polygram. This completes the display of the symbol and at the output of element 20 And under the influence of signals from the fourth output of the shift register 6 and the output of element 17 AND, the signal End of reflection is extracted. Simultaneously with the formation of micropigram elements, bus 34 from the second output of register 9 receives the Illumination Code, which is synchronized by the signals from the output of element 23 OR. In accordance with this code, only those micropigram elements that make up the contour of the displayed symbol are highlighted. . So, for seventeen to twenty microfacts (the polygram is posed) (It is possible to display a higher-quality alphanumeric alphabet to a number of arbitrary symbols. The information display time was reduced at the same information costs as the known device. With The solution of this problem in the usual way would require 68 bits of information per symbol. In the proposed device, the achieved effect is provided with 20 bits of information per symbol. The proposed device reduces the time of formation of symbols with improved and the quality of the displayed information, which also increases the reliability of the information generated and readable by the operator.A invention The device for displaying information on a CRT screen, containing a register, a pulse generator.The first shift register, drivers of X and Y deviating voltages, switch, elements And and OR, inverters (characterized in that, in order to improve speed and improve the quality of the displayed information, the device with. holds the second shift register, the input of which is connected to the output of the first element OR, the inputs of which are connected with the outputs of the first, second and three. the third And elements, the third shift register v, the installation input of which is connected to the input of the first shift register, the control input of the register and the output of the second OR element, the fourth shift register, the installation input of which is connected to the first input of the fourth And element and the output of the first OR element, a shift register, the outputs of which are connected to the first inputs of the switch, and two delay elements, the output of the pulse generator connected to the first; the inputs of the first, fifth and sixth And elements directly and through the First and second delay elements with control of the inputs of the third and fourth shift registers, the inputs of the second OR element are connected to the outputs of the fourth fifth and seventh elements And, the outputs of the first and fourth bits of the first register the shear through the driver of the deflecting voltage along the X coordinate is connected to the second input of the switch I directly and through i1 Schertor, the third inputs of the switch are connected directly and through the second inverter to the generator ers otkpon yuvdh voltages on those korrdina Y input KOjroporo podklyuchega shdhodam to the third and fourth members. IPI the first input of the third INR element is connected to the output of the first bit of the second shift register, and the second input is connected to the second input of the fourth element AND the output of the fifth bit of the second shift register, the output of the second and third bit of which is connected to the inputs of the fourth element OR, and the output of the fourth bit is with the first inputs of the second and third And elements, the output of the Second bit of the third shift register is connected to the second input of the sixth And element, the third input of which is connected to the output of the eighth And element, and the output is to the first input of the seventh element And and the second input of the third element And, the outputs of the third bits of the first and third shift registers are connected to the second inputs of the seventh and fifth elements And. correspondingly, the most significant bit of the fourth shift register is connected to the input of the first element AND, the second input of the second element AND, with the output of the fifth element AND, and the inputs of the second and third element And connected to the output of the ninth element AND, the input five the shift register is connected to the first input 5 1 of the tenth element AND and the output of the fourth element j, and the most significant bit of the fifth shift register is connected to the input of the tenth element And, the register outputs are connected to the inputs of the eighth and ninth elements AND, 8 1 Sources of Inform tion, .prin Tide into account in the examination 1.Govorov B.C. Picked up machine solutions on EDT screens. M. Owls. radio, 1975. 2. USSR author's certificate in application 2617547 / 18-24, cl. G 06 K 15/20, 05.22.78. FIG.