KR890004553A - Image Removal Mixer Using Double Gate FET - Google Patents

Image Removal Mixer Using Double Gate FET Download PDF

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Publication number
KR890004553A
KR890004553A KR870009547A KR870009547A KR890004553A KR 890004553 A KR890004553 A KR 890004553A KR 870009547 A KR870009547 A KR 870009547A KR 870009547 A KR870009547 A KR 870009547A KR 890004553 A KR890004553 A KR 890004553A
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KR
South Korea
Prior art keywords
fet
gate
output
mixer
input
Prior art date
Application number
KR870009547A
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Korean (ko)
Other versions
KR900004032B1 (en
Inventor
전순익
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR1019870009547A priority Critical patent/KR900004032B1/en
Publication of KR890004553A publication Critical patent/KR890004553A/en
Application granted granted Critical
Publication of KR900004032B1 publication Critical patent/KR900004032B1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/38Transmitter circuitry for the transmission of television signals according to analogue transmission standards
    • H04N5/40Modulation circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/20Adaptations for transmission via a GHz frequency band, e.g. via satellite

Abstract

내용 없음.No content.

Description

이중게이트의 FET를 이용한 이미지 제거 혼합장치Image Removal Mixer Using Double Gate FET

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 종래의 블럭구성도.1 is a conventional block diagram.

제 2 도는 본 발명의 블록구성도.2 is a block diagram of the present invention.

제 3도는 제 2 도의 회로 구성도.3 is a circuit diagram of FIG.

Claims (2)

3, 7―4, 2 GHZ의 입력신호를 받아들이는 입력신호단(20)에 입력신호가 양분되면서 각각의 위상이 변화하도록 90° 혼합결합기(5)의 입력단을 연결하고, 상기 90° 혼합결합기(5)의 입력단에 원하지 않는 신호가 반사되어 되돌아가지 않도록 50Ω을 갖는 정합용저항(R1)을 연결하고, 상기 90° 혼합결합기(5)의 출력단에는 2개의 신호를 받아 주파수를 변환시킬수 있도록 이중게이트의 전계효과트랜지스터(FET1)(FET2)의 게이트(G1)측을 연결하고, 그의 게이트(G2)측에는 전력의 위상이 차이가 나지않도록 전력이분배기(6)를 연결 함과 더불어 상기 이중게이트의 전계효과 트랜지스터(FET1)(FET2)의 드레인(D)측에는 저역통과 필터부(7)(7′)의 입력단을 각각 연결하고, 상기 지역통과 필터부(7)(7′)의 출력단에는 90° 혼합결합기(5′)를 연결하되 상기 90° 혼합결합기(5′)의 출력단에는 50Ω을 갖는 정합용저항(R2)을 연결하여 구성됨을 특징으로 하는 이중 게이트의 FET를 이용한 이미지 제거혼합장치.The 90 ° mixed combiner (5) is connected to the input signal stage (20) which receives the input signals of 3, 7-4, and 2 GHZ so that the respective phases change while the input signals are divided into two. Connect the matching resistor (R 1 ) with 50Ω to the input terminal of (5) so that the unwanted signal is not reflected and return.The output terminal of the 90 ° mixer (5) receives two signals so that the frequency can be converted. The gate (G 1 ) side of the field effect transistor (FET 1 ) (FET 2 ) of the double gate is connected, and the power divider (6) is connected to the gate (G 2 ) side of the gate so that the phase of the power does not differ. In addition, the input terminal of the low pass filter unit 7 (7 ') is connected to the drain (D) side of the field effect transistor (FET 1 ) (FET 2 ) of the double gate, respectively, and the local pass filter unit (7) (7) 90 'at the output An image removal mixing device using a double-gate FET characterized in that a mixing coupler (5 ') is connected, but a matching resistor (R 2 ) having 50 kW is connected to the output terminal of the 90 ° mixing coupler (5'). . 제 1 항에 있어서, 입력신호단(20)과 50Ω을 갖는 정합용 저항(R1)에 2개의 50Ω, 35.4Ω의 스트립선로와 각각의 λ/4의 길이를 가진 90° 혼합결합기(5)의 입력단을 연결함과 더불어 상기 90° 혼합결합기(5)의 출력단에는 λ/4길이를 가진 직류차단결합기(12)를 설치하고, 상기 직류차단결합기(12)의 타단에는 70.7Ω과를 λ/4를 가진 길이와 갈라진 양단사이에 100Ω을 갖는 정합용 저항(R3)을 결합시켜 반사되는 신호가 제거되도록 전력 이분배기(6)를 설치하고, 상기 전력 이분배기(6)의 출력단에는 발진신호를 발생시킬수 있도록 전압제어발진기(9)를 연결하고, 상기 직류차단결합기(12)와 전력이분배기(6)의 양단에는 이중 게이트의 전계효과트랜지스터 (FET1)(FET2)의 게이트(G1)(G2)측을 각각 연결하고 상기이중 게이트의 전계효과트랜지스터(FET1)(FET2)의 드레인(D)측에는 바이어스전압부(10)(10′)와 저역통과필터부(7)(7′)의 입력단을 연결 구성하고, 상기 저역통과 필터부(7)(7′)의 출력단에는 90° 혼합결합기(5′)를 통하여 상기90° 혼합기(5′)의 출력단에는 50Ω을 갖는 정합용저항(R2)과 중간주파수증폭부(11)를 연결하여 구성됨을 특징으로 하는 이중게이트의 FET를 이용한 이미지 세거혼합장치The 90 ° mixed-coupler (5) according to claim 1, having two 50 kW, 35.4 kW strip lines and a respective length of? / 4 with two input resistors 20 and a matching resistor R 1 having 50 kW. In addition to connecting the input terminals of, the output of the 90 ° mixer (5) is provided with a DC circuit breaker (12) having a length of λ / 4, and the other end of the DC circuit breaker (12) is 70.7Ω and λ / A power divider (6) is provided so as to remove the reflected signal by coupling a matching resistor (R 3 ) having a 100 사이 between the length having 4 and the split ends, and the oscillation signal at the output of the power divider (6). to the sikilsu occurs connecting the voltage-controlled oscillator 9, and the direct current cut coupler 12 and the electric power that both ends of the distributor (6) has a field-effect transistor of the dual gate (FET 1), the gate of the (FET 2) (G 1 ) (G 2 ) connect the sides and double The input terminal of the bias voltage section 10 (10 ') and the low pass filter section (7) (7') is connected to the drain (D) side of the field effect transistor (FET 1 ) (FET 2 ) of the gate. A matching resistor (R 2 ) and an intermediate frequency amplifier section having a 50 2 at the output of the 90 ° mixer (5 ') through a 90 ° mixer (5') at the output of the pass filter (7) (7 '). 11) Image segmenter mixing device using double gate FET ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870009547A 1987-08-31 1987-08-31 Image reducing and mixing device using double - gate fet KR900004032B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870009547A KR900004032B1 (en) 1987-08-31 1987-08-31 Image reducing and mixing device using double - gate fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870009547A KR900004032B1 (en) 1987-08-31 1987-08-31 Image reducing and mixing device using double - gate fet

Publications (2)

Publication Number Publication Date
KR890004553A true KR890004553A (en) 1989-04-22
KR900004032B1 KR900004032B1 (en) 1990-06-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870009547A KR900004032B1 (en) 1987-08-31 1987-08-31 Image reducing and mixing device using double - gate fet

Country Status (1)

Country Link
KR (1) KR900004032B1 (en)

Also Published As

Publication number Publication date
KR900004032B1 (en) 1990-06-09

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