KR890003487B1 - Low table addressing circuit by low grade drt controler - Google Patents

Abstract

The CRT display comprises a CPU (1), a CRT controller (2), a multiprocessor (3), video RAMs (4,5) and bidirectional buffers (6,7). The scan-line address outputs (RA0-3) of the CRT controller (2) are connected to a decorder (11) which detects the latest scan line. The output terminal (Y5) of a decorder (11) provides the signal to a counter (12) which instigates PROM (15) which generates row-table addressable control signals for sequential CRT controller.

Description

Low Table Addressing Circuit Using Low-end CRT Controller

1 is a block diagram showing a low table addressing circuit using a lower CRT controller according to the present invention.

2 is a control signal generation circuit diagram according to the present invention.

3 and 4 Donzen This is a timing chart for explaining a low table addressing circuit using a low-end CRT controller according to the present invention.

* Explanation of symbols for main parts of the drawings

1: central processing unit 2: CRT controller

3: Multiplexer 4, 5: Video RAM (Data RAM, Attribute RAM)

6, 7: interactive buffer 11: decoder

12, 14: counter 13, 17, 18: D flip-flop

15: PROM 16: latch circuit

IV _{1 to} IV ₄ : Inverter OR _{1 to} OR ₄ : OR gate

RA ₀ ~RA _3: Scanning line address VSYNC: vertical synchronization signal

DE: Display enable signal HALT: Enable stop signal

CCLK: Character Clock

Industrial use

The present invention provides a CRT display control device including a low-level CRT controller, wherein when a computer outputs a character output on a CRT screen, the computer terminal reduces the time for accessing the CRT display control device from the central processing unit. The present invention relates to a low table addressing circuit using a low level CRT controller in which a control signal generation circuit is added to a low level CRT controller to improve low data addressing.

Conventional Technology and Problems

In general, the raster scan method is widely used as a method of displaying characters on a CRT terminal of a terminal device of a computer, which is repeatedly and continuously displayed on a CRT screen by a CRT controller, which is a dot pattern of characters. It is the same effect that the text is scanned and written on the CRT screen. In order to display characters on the screen of the CRT by using the CRT controller, a memory for storing the character codes is needed so that the CRT controller can repeatedly output the code data for the characters. It's called RAM. In other words, the video RAM outputs code data of characters input from the keyboard or computer according to the address repeatedly designated by the CRT controller to display characters on the screen of the CRT. As described above, when the code data of the characters input from the keyboard or the computer is input to the video RAM, the central processing unit is controlled. Thus, the central processing unit and the CRT controller share the video RAM and access the central processing unit. The data processing efficiency of a computer terminal device depends on the access time of the video RAM. That is, the longer the access time of the CRT display control device from the central processing unit, the lower the data processing efficiency of the computer terminal device. For example, if you want to remove one line from the screen or add a new line, In the central processing unit for CRT display control, because the processing unit has to remove data for one row from the video RAM of the CRT display control device or record data for one row in the video RAM and then move the data storage location of the remaining rows. The data processing efficiency of the computer terminal device is further deteriorated since the character code data is delayed by the time for transferring.

However, as described above, there are two methods of addressing the video RAM accessed and shared by the CRT controller and the central processing unit. Each of the two methods will be described. As follows.

First, the sequential addressing method mainly uses a low-end CRT controller. When the address is supplied to the video RAM by the CRT controller, the entire address signal for one screen is sequentially supplied. In the sequential addressing method using the low-end CRT controller, the video RAM, which is symmetrical to the screen of the CRT and 1: 1, is sequentially addressed from the memory address start designated register built in the CRT controller. If the RAM is as many as one line of text displayed on the screen of the CRT, for example, one page, the maximum number of 12 lines must be moved when adding or deleting one middle line of text displayed on the CRT screen. Although it does not greatly affect the processing efficiency, if the video RAM is composed of two or more pages, the entire page must be moved in addition to the above 12 lines, which in turn causes a significant decrease in the data processing efficiency of the computer.

On the other hand, the low table addressing method is to improve the data processing efficiency of the computer terminal device by improving all the problems that come from the sequential addressing method using the low-end CRT controller described above, and the order of the rows to be displayed on the screen of the CRT. Is set as a ROW Table, and when the CRT controller accesses the video RAM from the first address of each row by sequentially accessing the row table, the data of each row of the video RAM is output and displayed on the screen of the CRT. Characters are displayed in the order of the rows along the row table. Therefore, if you want to remove the character line on the CRT screen or insert the character line, you just need to adjust the address of the corresponding line in the row table without changing the contents of the video RAM. The access time is shortened, and even if the video RAM is composed of two or more pages, if the character line needs to be changed, only the low table needs to be adjusted, thereby improving the data processing efficiency of the computer terminal device. In order to realize such a low table addressing, first, a register to store the head address of each row is required, and an interrupt signal is required to distinguish each row. The advanced CRT controller includes such circuits, so that sequential addressing is performed. In addition, low table addressing can be realized. However, these high-end CRT controllers are expensive and include functions that are not necessary for simple computer terminal devices, resulting in many inefficiencies in producing products.

As described above, according to the present invention, data to be recorded on the CRT controller is recorded in an undisplayed portion of the video RAM, and when one line of characters is displayed, the data recorded in the video RAM is recorded in accordance with a control signal by the PROM. By enabling low table addressing, the low cost CRT controller can be manufactured at low cost using low quality CRT controllers.

In view of the above circumstances, the present invention has been invented by connecting a low-end CRT controller with a circuit for detecting each character line, a counter for counting character lines, and a PROM for storing data for row table addressing. When the display of the character line is finished, change the data of the memory start timing register in the CRT controller, and reset the CRT controller before starting character display to specify the video RAM from the address of the memory start designated register to the low-end CRT controller. It is an object of the present invention to provide a low table addressing circuit using a low-end CRT controller capable of low table addressing.

Composition of the Invention

The present invention for achieving the above object, the CRT display comprising a central processing unit (1) and a CRT controller (2), a multiplexer (3), video RAM (4, 5) and the two-way buffer (6, 7) In the control apparatus, the decoder 11 for detecting the last scan line of one row is connected to the scan line address output terminals RA _{0 to} RA ₃ of the CRT controller 2, and the output terminal Y of the decoder 11 is connected. ₅ ), a counter 12 in which the inverter IV ₁ counts the number of rows per page, a NAND gate ND ₁ for detecting the last row, and a D-type flip-flop 13 for generating an interrupt signal NMI, in turn. In addition, the counter 14 is connected via OR gates OR ₁ and OR ₂ , and a PROM 15 outputting a control signal for low table addressing to the output terminals A to D of the counter 14. The input terminal of the CRT controller 2 is connected to the output terminals D _{0 to} D ₃ of the PROM 15 via a latch circuit 16. CS, RS, RESET) and the enable signal input terminal EN of the bidirectional buffers 6 and 7 are respectively connected, and the D type flip-flop 17 and the inverter are connected to the output terminal Q ₃ of the latch circuit 16. The PROM 15 and the OR gate OR ₃ are connected via (IV ₂ ), respectively, and the D-type flip is connected to the CRT controller 2, the display enable signal output terminal DE, and the vertical synchronous signal output terminal VSYNC. The counter 12 and the D flip-flop 13 are connected to each other via the flop 18.

Reference numeral CCLK denotes a character clock, and HALT denotes an enable stop signal of the central processing unit 1.

Action

Referring to the operation of the present invention configured as described above are as follows.

1 is a block diagram showing a state in which each control signal according to the present invention is supplied to a commonly used CRT display control device, wherein the address bus of the central processing unit 1 and the CRT controller 2 is a character clock The multiplexer 3, which operates in synchronism with the CCLK, is transmitted to the video RAM composed of the data RAM 4 and the attribute RAM 5. When the character clock CCLK is at a low level, the CRT controller 2 ) Is transmitted to the video RAMs 4 and 5 through the multiplexer 3, and the address of the central processing unit 1 is transmitted to the video RAMs 4 and 5 when the character clock CCLK is at a high level. It is. In addition, the data buses of the central processing unit 1 and the CRT controller 2 are commonly used, and are connected to the video RAMs 4 and 5 through the bidirectional buffers 6 and 7. That is, in order to record data in the data RAM 4 and the attribute RAM 5 of the video RAM in the central processing unit 1, the enable signal EN of the bidirectional buffers 6 and 7 is set to a low level and is bidirectional. When the direction pins DIR of the buffers 6 and 7 are adjusted to "0", the bidirectional buffers 6 and 7 open from the central processing unit 1 to the video RAM 4 and 5 to record data. On the contrary, in order to read the data of the video RAMs 4 and 5 from the central processing unit 1, the direction pin DIR applied to the bidirectional buffers 6 and 7 may be adjusted to "1".

On the other hand, in order to record data in the CRT controller 2, a low-level signal is supplied to the chip select stage CS and the register select stage RS of the CRT controller 2 to supply the CRT controller 2 through the data bus. After data is written to the address selection register in < RTI ID = 0.0 > 1), < / RTI > At this time, the address selection register and the data register of the CRT controller 2 are latched into the CRT controller 2 when the write / read signal R / W goes from the low level to the high level. When the low level signal is applied to the reset terminal RESET of the CRT controller 2, all the counter values in the CRT controller 2 are cleared. When the high level signal is applied, the scan line addresses RA _{0 to} RA ₃ are The count starts from 0 and the memory address starts counting from the data recorded in the memory start designated register.

In order to display the characters on the screen of the CRT using the CRT display control device as described above, a control signal generation circuit as shown in FIG. 2 is configured. same.

The decoder 11 is installed to detect the last scan line among the programmed scan lines per row. For example, if the program is programmed with 14 scan lines per scan line, the scan line addresses RA _{0 to} RA ₃ are the last scan lines. the output terminal of the decoder 11 when the 1101 (Y ₅₎ because it represents the output (Y ₅₎ are to fall to the low level one line has ended in the bar, the decoder 11, which falls to the low level, the inverter (ⅳ ₁₎ Through this, the counter 12 for counting the text lines displayed on the screen of the CRT is increased by one. Therefore, each time the row changes, the counter 12 is incremented by one.

In addition, if the display enable signal DE drops to a low level after the last scan line of the last row of the characters displayed on the CRT screen is scanned, the initial state of the OR gate OR ₃ is low, so that the D of the counter 14 The type flip-flop 17 is cleared and one output terminal Q of the D-type flip-flop 17 is at a high level, and the RESET terminal of the counter 14 is provided through the OR gate OR ₃ and the OR gate OR ₂ . By resetting the counter 14 to a high level, the counter 14 is synchronized by the character clock CCLK and incremented by one.

As described above, as the counter 14 starts counting, an address is supplied to the PROM 15, and data output from the PROM 15 is supplied to the latch circuit 16 to mediate the inverter IV ₃ . The latch circuit 16 latches the latch clock 16 in synchronization with the character clock CCLK.

In this way, the data programmed at the addresses 1 to 15 of the PROM 15 are synchronized with the character clock CCLK and supplied to the CRT controller 2 and the bidirectional buffers 6 and 7 as control signals. Since the data at address 15 causes the output terminal Q ₃ of the latch circuit 16 to be at a low level, the D-type flip-flop 17 is preset so that an address larger than 16 is supplied to the PROM 15. (IV ₂ ), the output of the OR gate OR ₃ continues to the high level. However, more than 16 address data of the PROM (15), so the output (D3) of the PROM (15) is programmed to the high level and then kaeraekteo clock output terminal (D ₃₎ of the latch circuit 16 when (CCLK) is entered the The low level signal during one character clock period is used as the reset signal of the CRT controller 2, and when the CRT controller 2 is reset by the reset signal, the decoder 11 Since the output terminal Y ₅ is at the high level, the output of the OR gate OR ₂ continues to be at the high level. When the counter 12 that counts the character rows counts as many as the number of rows programmed in one page, the output signal of the NAND gate ND ₁ becomes low level, and the D-type flip-flop 13 is preset so that the interrupt signal ( NMI is generated. When this interrupt signal NMI is generated, the output signal of the OR gate OR ₂ is maintained at a high level. Thus, the counter 14 and the D flip-flop 17 described above are cleared. Can be prevented.

Therefore, if the total number of lines of the screen to be programmed to be programmed in the CRT controller is programmed to be one line, the last character line is displayed, so that one line is displayed and then vertically reverted without being reset.

On the other hand, when the vertical synchronization signal VSYNC becomes low level, the D-type flip-flop 18 is cleared so that the counter 12 is reset, and after the vertical synchronization signal VSYNC becomes high level, the display enable signal DE ) Is high level, the output terminal (Q) of the D-type flip-flop 18 is a high level, the high-level signal is applied to the D-type flip-flop 13 as a clock signal, the interrupt is released and accordingly the operation described above. Will be repeated.

This operation will be described in more detail based on the timing charts of FIGS. 3 and 4 as follows.

When the display enable signal DE goes low and the output terminal Y ₅ of the decoder 11 goes low, the enable loop signal HALT is applied to the central processing unit _{1 with the} OR gate OR ₁ as a medium. ) Is supplied to the central processing unit 1 and the operation stop state 4, and then supplied to the bidirectional buffers 6 and 7 of the control signal EN, which is the output of the latch circuit 16, to the bidirectional buffers 6 and 7. ) Is opened from the video ram 4 and 5 to the central processing unit 1. At this time, since the data output terminal of the central processing unit 1 is in the high impedance state, the data of the video RAMs 4 and 5 are recorded in the CRT controller 2.

The data recording to the CRT controller 2 is performed by the low level of the write / read signal R / W equivalent to the CRT controller 2 by the control signal CS and the character clock CCLK. In this case, the CRT controller Data is written to the address selection register and the data register by the register selection signal RS supplied to (2).

In this manner, after data is written to the memory start designated register of the CRT controller 2, the CRT controller 2 is reset when the output terminal Q ₃ of the latch circuit 16 becomes low level, and then the scan line is reset. The memory address at which the addresses RA _{0 to} RA ₃ start counting from zero starts counting from the address recorded in the memory start designation register.

When the CRT controller 2 is reset, the scan line addresses RA _{0 to} RA ₃ become 0 and the output terminal Y ₅ of the decoder 11 becomes high level, which is supplied to the central processing unit 1. The EABLE STOP signal HALT is removed to start the CPU 1.

As a result, in the last scan line of one row, the memory area of the video RAM 4 and 5, which is not displayed on the screen of the CRT, is used as the data storage location of the CRT controller 2, and the low table addressing is performed with the control signal by the PROM 15. It will be done.

Claims (1)

A CRT display control device comprising a central processing unit (1), a CRT controller (2), a multiplexer (3), a video RAM (4, 5), and an interactive buffer (6, 7), wherein the CRT controller (2) The decoder 11 which detects the last scan line of one character line is connected to the scan line address output stages RA _{0 to} RA ₃ , and the inverter IV ₁ and 1 are connected to the output stage Y ₅ of the decoder 11. The counter 12 for counting the number of rows per page, the NAND gate ND ₁ for detecting the last row, and the D-type flip-flop 13 for generating the interrupt signal NMI are connected in sequence, and the OR gate OR ₁ , The counter 14 is connected via OR ₂ ), and the output terminals D _{0 to} D _{3 of} the counter 14 are connected to the input terminals CS, RS, and RESET of the CRT controller 2 through the latch circuit 16. And an enable signal input terminal EN of the bidirectional buffers 6 and 7 are connected to each other, and an output type Q ₃ of the latch circuit 16 is connected to a D-type flip-flop 17 and an inverter ( The PROM 15 and the OR gate OR ₃ are connected to each other via IV ₂ ), and the D-type flip-flop is connected to the display enable signal output terminal DE and the vertical synchronous signal output terminal VSYNC of the CRT controller 2. 18) Low table addressing circuit using a low-end CRT controller, characterized in that the counter 12 and the D-type flip-flop (13) is connected to the low table addressing.

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