KR870006469A - Low Table Addressing Circuit Using Low-Level CRT Controller - Google Patents

Low Table Addressing Circuit Using Low-Level CRT Controller Download PDF

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Publication number
KR870006469A
KR870006469A KR1019850010012A KR850010012A KR870006469A KR 870006469 A KR870006469 A KR 870006469A KR 1019850010012 A KR1019850010012 A KR 1019850010012A KR 850010012 A KR850010012 A KR 850010012A KR 870006469 A KR870006469 A KR 870006469A
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KR
South Korea
Prior art keywords
low
crt controller
output terminal
counter
flop
Prior art date
Application number
KR1019850010012A
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Korean (ko)
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KR890003487B1 (en
Inventor
최천일
Original Assignee
정재은
삼성전자 주식회사
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Priority to KR1019850010012A priority Critical patent/KR890003487B1/en
Publication of KR870006469A publication Critical patent/KR870006469A/en
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Publication of KR890003487B1 publication Critical patent/KR890003487B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

내용 없음.No content.

Description

저급 CRT 콘트롤러를 이용한 로우테이블 어드레싱회로Low Table Addressing Circuit Using Low-Level CRT Controller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 블록도.1 is a block diagram according to the present invention.

제2도는 본 발명에 따른 제어신호 발생회로도.2 is a control signal generation circuit diagram according to the present invention.

제3도 및 제4도는 본 발명에 따른 타이밍 차트이다.3 and 4 are timing charts in accordance with the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 중앙처리 장치 2 : CRT 콘트롤러1: central processing unit 2: CRT controller

3 : 멀티플렉서 4,5 : 비디오램(데이터램, 어트리튜트램)3: Multiplexer 4,5: Video RAM (Data RAM, Attitude RAM)

6,7 : 쌍방향버터 11 : 디코더6,7 bidirectional butter 11 decoder

12,14 : 카운터 13,17,18 : D플립플롭12,14 Counter 13,17,18 D flip flop

15 : 프로그램 16 : 롬랫치회로15: Program 16: Lom latch circuit

IV1-IV1: 인버터 OR1-OR4: 오아게이트IV 1 -IV 1 : Inverter OR 1 -OR 4 : Oagate

RA0-RA3: 스캔라인 어드레스 VSYNC : 수직동기신호RA 0 -RA 3 : Scan line address VSYNC: Vertical sync signal

DE : 표시동작신호 HALT : 동작중지신호DE: Display operation signal HALT: Operation stop signal

CCLK : 캐랙터클록CCLK: Character Clock

Claims (1)

중앙처리장치(1)와 CRT 콘트롤러(2), 멀티플렉서(3), 비디오램(4)(5)및 쌍방향버퍼(6)(7)등을 구비하여 구성된 CRT 표시제어장치에 있어서, 상기 CRT 콘트롤러(2)의 스캔라인 어드레스출력단(RA0-RA3)에다 1문자행의 마지막스캔라인을 검출하도록 디코더(11)를 연결하고, 상기 디코더(11)의 출력단(Y5)에는 인버터(IV1)와 1페이지당 행수를 카운트하는 카운터(12), 마지막행을 검출하는 낸드게이트(ND1)및 인터럽트신호(IV1)를 발생하는 D플립플롭(13)을 차례로 연결함과 더불어 오아게이트(OR1)(O2)를 차례로 매개하여 카운터(14)를 연결하며, 카운터(14)의 출력단에(A-D)는 로우테이블어드레싱을 위한 제어신호를 출력시키는 프로그램롬(15)을 연결하고, 상기 프로그램롬(15)의 출력단(D0-D3)에는 랫치회로(16)를 매개하여 CRT 콘트롤러(2)의 입력단(CS)(RS)(RESET)과 상기 버퍼(6)(7)의 이네이블신호입력단(EN)을 각각 연결하여, 상기 랫치회로(16)의 출력단(Q3)에는 D플립플롭(17)과 인버터(IV2)를 각각 매개하여 상기 프로그램롬(15)과 오아게이트(OR3)를 연결하고, 상기 CRT 콘트롤러(2)의 표시동작신호출력단(DE)과 수직동기신호출력단(VSYNC)에는 D플립플롭(18)을 매개하여 상기 카운터(12)와 D플립플롭(13)을 연결하여서, 로우테이블어드레싱을 하도록 된 것을 특징으로하는 저급 CRT 콘트롤러를 이용한 로우테이블 어드레싱회로.A CRT display control device comprising a central processing unit (1), a CRT controller (2), a multiplexer (3), a video RAM (4), a five-way buffer (6), and the like. The decoder 11 is connected to the scan line address output terminal RA 0 -RA 3 of (2) to detect the last scan line of one character line, and the inverter IV 1 is connected to the output terminal Y 5 of the decoder 11. ), A counter 12 for counting rows per page, a NAND gate (ND 1 ) for detecting the last row, and a D flip-flop (13) for generating an interrupt signal (IV 1 ). OR 1 ) (O 2 ) in turn to connect the counter 14, the output (AD) of the counter (14) is connected to the program ROM (15) for outputting a control signal for low table addressing, and output terminals of the program ROM (15) (D 0 -D 3 ) , the input terminal (CS) (RS) (RESET) and the member of the latch circuit 16 to the CRT controller parameters (2) (6) (7) of the enable to connect the signal input terminal (EN), respectively, the latch circuit 16 of the output terminal (Q 3), the D flip-flop 17 and the inverter (IV 2) the respective parameter to the program The ROM 15 is connected to the OR gate OR 3 , and the counter operation signal is connected to the display operation signal output terminal DE and the vertical synchronous signal output terminal VSYNC of the CRT controller 2 by a D flip flop 18. 12) A low table addressing circuit using a low-end CRT controller, characterized in that low table addressing is performed by connecting the D flip-flop (13). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850010012A 1985-12-30 1985-12-30 Low table addressing circuit by low grade drt controler KR890003487B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850010012A KR890003487B1 (en) 1985-12-30 1985-12-30 Low table addressing circuit by low grade drt controler

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850010012A KR890003487B1 (en) 1985-12-30 1985-12-30 Low table addressing circuit by low grade drt controler

Publications (2)

Publication Number Publication Date
KR870006469A true KR870006469A (en) 1987-07-11
KR890003487B1 KR890003487B1 (en) 1989-09-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850010012A KR890003487B1 (en) 1985-12-30 1985-12-30 Low table addressing circuit by low grade drt controler

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KR (1) KR890003487B1 (en)

Also Published As

Publication number Publication date
KR890003487B1 (en) 1989-09-22

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