KR890001897B1 - Modulation circuit of digital audio tape - Google Patents

Abstract

The circuit modulates and devides binary coded digital data for multitrack type recording, up-grading record density, removing blanking time. The 10-bit converted data is transmitted serially through P/S and recorded to the track by latch (25). Each modulation unit (20) comprises mutual-inverse driving buffers (21), (22) and sink generators (23), (24) to read and write signals.

Description

Multitrack Modulation Circuits of Digital Audio Equipment

1 is a block diagram of data recording of a digital audio apparatus.

2 is a state diagram of data recorded on a tape in a multitrack manner.

3 is a circuit diagram of the present invention.

4 is a control circuit for driving a circuit diagram of the present invention.

5 is a time chart of each part of the circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

10: multitrack modulation circuit 12: binary counter

13: Decimal Counter 14: Decoder

FF ₁ : flip-flops A ₁ , A ₂ , A ₃ ,. Endgate

OR ₁ , OR ₂ , OR ₃ ,... : Oagate P / S: Parallel series circuit

BU ₁ , BU ₂ ,... BU ₁₀ : 3-state buffer 20: Modulator

21, 22: frame buffer 23, 24: sync generator

25: Latch

The present invention relates to a multitrack modulation circuit of a digital audio device used for recording a digital signal processed audio signal on a tape. Digital audio equipment converts analog signals into digital signals and processes them so that errors can be easily compensated for during playback, so that sound can be reproduced close to the original sound. There is an advantage to this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multitrack modulation circuit capable of modulating signal processed digital data to record data on a tape in a multitrack manner, thereby effectively recording and recording density on a tape by effectively modulating and separating the signal processed data. It is possible to remove the blanking time while increasing the.

This will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of data recording of a digital audio device. The analog audio signal is converted into a digital state signal through an analog digital converter 1 to generate four parities that can be corrected by the first encoder 2. The multi-track modulation circuit 10 generates two parities in the second encoder 4 through the interleave 3, converts 8-bit data into 10-bit data in the data conversion table 5, and applies a state signal in parallel. Is converted to serial and then written to the tape as multitrack (track1-track10).

At this time, when performing multi-track modulation for sync compensation, a sync (sync) signal is needed to accurately find each data loaded on the tape. After (10 bits) are recorded, the status signal (140 bits) is recorded so that the original sound can be reproduced correctly during reproduction.

The third turn is a data state signal applied from by 10-bit data conversion table 5, a circuit diagram of the present invention transferred in series via the bottle, a series circuit (P / S), each of the three-state buffers (BU _1, BU ₂ ,... BU ₁₀ ) and the multi-stage modulator 20 are configured to be recorded on each track of the tape through the latch 25. Each modulator 20 is configured to transmit to the frame buffer 21, 22. latch to configure the sync generator 23, 24 via the read (read) and a write (write) when the aND gate after reciprocal drive configured (a ₁₎ (a ₂₎ and Iowa gate (OR ₁₎ ( It is configured to be applied to 25).

Inverting the input terminal of the AND gate A ₁ is to prevent a malfunction when the drive and write of the frame buffers 21 and 22 are reversely driven.

FIG. 4 is a control circuit diagram capable of driving FIG. 3, and the output of the binary counter 12 to which a clock signal of 40 KHZ is applied is shown in FIG. 5 through the ora gate OR ₃ and the AND gate A ₁₀ . The control pulse CTB as shown in FIG. 5 outputted from the oragate OR ₃ is generated as the clock signal of the 12-counter counter 13 to perform the 12-degree counting. The outputs Q ₁ -Q ₃ of the decimator counter 13 are applied to the decoder 14 while the output Q ₃ is applied to the flip flop FF ₁ through the inverter I ₁ as shown in FIG. 5. It is configured to output each block control pulse (CTC).

The frame (CT ₁ -CT ₁₀ ) output to output as shown in FIG. 5 by the decoder 14 to which the output of the decimator counter 13 is applied is the AND gate (A ₃ -A ₈ ) and the oragate (OR ₂ ) (OR _{It is} configured to generate a control pulse (CTF) (CTG) through ₃ ).

The AND gate A ₉ is configured to output the control pulse CTD as shown in FIG. 5 by applying the control pulse CTB, the inverted control pulse CTA, and a pulse of 800 KHZ. At this time, the output control pulse CTD is used as a clock pulse when the frame buffers 21 and 22 are written.

The circuit diagram of the present invention of FIG. 3 configured as described above will be described in detail based on the waveform of FIG. 5 generated by the control circuit diagram of FIG. First, a multi-track modulation circuit 10 according to the present invention is applied with a state signal obtained by converting an 8-bit data signal into a 10-bit signal in the data conversion table 5 as shown in FIG. 1. To record the respective track data.

As described above, the 10-bit parallel data (1 codeword) signal processed by the data conversion table 5 is applied to the control circuit CTA as shown in FIG. When input, the 10-bit parallel data input is a signal-processed 10-bit long codeword unit, and one codeword value is maintained for 25 μs.

After 14 consecutive codewords are input, no data is input for 50μs, and this period (14 x 52μs + 50μs = 400μs) becomes one frame.

That is, one frame of data is input during one period (400 μs) of the control pulse (CTB) shown in the time chart of FIG. It doesn't work.

That is, one block (BLOK) is constituted as a signal for which no data is recorded while 10 frames of data corresponds to 2 frames for 4800 µs, and data signals in block units are continuously input.

Therefore, in the case that data in block unit as shown in FIG. 5 is inputted, in a serial circuit P / S, a 10-bit parallel data signal is serially shifted internally by a control pulse CTA as shown in FIG. 5 applied as a clock signal. The data signal is converted into the three-state buffers BU ₁ , BU ₂ ,... BU ₁₀ sequentially.

In the three-state buffers BU ₁ , BU ₂ ,... BU ₁₀ , the data inputted in series by the frame pulses CT ₁ , CT ₂ ... CT _{10 as} shown in FIG. Each track data divided into) data is input to the frame buffers 21 and 22 of each modulator 20 configured for each of the three-state buffers BU ₁ , BU ₂ ,... BU ₁₀ .

Although only the modulator 20 for one track is shown in the figure, the modulator is configured in the same manner for the remaining tracks. That is, the modulator 20 should be substantially configured in each of the buffers BU ₁ , BU ₂ ,... BU ₁₀ .

The track data input to the frame buffers 21 and 22 is inputted when the A block data is input by the control pulse CTF (CTG) output by FIG. 4 (that is, when the block control pulse CTC is a high potential state signal). 5 is written to the frame buffer 21 by the control pulse CTD of FIG. 5, and at the time of B block data input, it is written to the frame buffer 22 by the control pulse CTD of FIG. The AND gate to which 140 bit (one frame) data written to the frame buffer 21 and the sync data of the sink generator 23 are successively read by the CTE to apply the block control pulse CTC of FIG. It is input to the latch 25 through the (A ₁ ) and the oragate (OR ₁ ).

Then, when the A block data is input again, the data is written to the frame buffer 21, and the data written to the frame buffer 22 and the sync data of the sink generator 24 are transferred to the AND gate A by the block control pulse CTC. ₂ ) and oragate (OR ₁ ) is input to the latch 25, so that each track timer at each input of the latch 25 has one frame of data (140 bits) and sync data (10 bits) for one block period. ) Is continuously input and in order to record it on the tape, a timer of each track is recorded on the tape by inputting a control pulse (CTE) as shown in FIG.

In other words, the data of each track is continuously applied to the latch 25 during one block, and data of one frame (140 bits) and sync data (10 bits) are continuously applied, and a control pulse (CTE) of FIG. By inputting to the latch 25, it is output to each track (track 1-track 10) of the tape, so that it is recorded on the tape through the head as shown in FIG. Here, the control pulse (CTE) is a clock pulse having a frequency of 31.25KHZ, which frequency is determined by the following calculation.

Data input time of 1 block = Data output time of 1 frame

4800μs = 150bit × T

In this case, 150 bits include 140 bits of data of one frame and 10 bytes of sync data of each frame.

As described above, the present invention inserts a sync signal into each track so that the recording position of the data can be sensed so as to increase the recording density of the tape by effectively using modulation and separation of the data when recording on the tape after multitrack modulation. It is possible to provide a multitrack modulation circuit of a digital audio device capable of eliminating blanking time.

Claims (1)

After the digital signal converted from the state data, the conversion table (5) through a parallel-to-serial circuit (P / S) via the respective modulator (20) connected to the 3-state buffers _{(BU 1, BU 2, ...} BU 10) Each modulator 20 is configured to be applied to the latch 25 and the frame buffers 21 and 22 and the sink generators 23 and 24 are driven in reverse with each other to read and write. A ₁ ) (A ₂ ) and a multitrack modulation circuit of a digital audio device configured to be output through an OR gate (OR ₁ ).

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