KR890001183A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
KR890001183A
KR890001183A KR1019880007311A KR880007311A KR890001183A KR 890001183 A KR890001183 A KR 890001183A KR 1019880007311 A KR1019880007311 A KR 1019880007311A KR 880007311 A KR880007311 A KR 880007311A KR 890001183 A KR890001183 A KR 890001183A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
insulating film
leads
semiconductor device
organic insulating
Prior art date
Application number
KR1019880007311A
Other languages
Korean (ko)
Other versions
KR960013778B1 (en
Inventor
도시유끼 사꾸다
가즈유끼 미아자와
사도시 오구찌
아이조우 가네다
마사오 미다니
쇼우조우 나까무라
구니히고 니시
겐 무라까미
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62161333A external-priority patent/JPH0777226B2/en
Priority claimed from JP62234654A external-priority patent/JP2567870B2/en
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR890001183A publication Critical patent/KR890001183A/en
Priority to KR1019920012675A priority Critical patent/KR970004216B1/en
Application granted granted Critical
Publication of KR960013778B1 publication Critical patent/KR960013778B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음No content

Description

반도체장치Semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예에 의한 수질 몰드 DIP 패키지의 전체구성을 도시하는 사시도.1 is a perspective view showing the overall configuration of a water-quality mold DIP package according to an embodiment of the present invention.

제2도는 및 제3도는 각각 제1도의 A-A선 및 B-B선에 따른 단면도.2 and 3 are cross-sectional views taken along lines A-A and B-B of FIG. 1, respectively.

Claims (8)

(a) 중앙부에 여러개의 본딩 패드를 갖는 직사각형의 반도체 칩, (b) 상기 반도체 칩 표면을 덮고, 상기 여러개의 본딩 패드부에 열림구멍을 갖는 유기 절연성피막, (c) 상기 절연성 피막상의 접착제층, (d) 상기 반도체 칩 표면의 절연성 피막상에 상기 접착제층을 거쳐서 접착된 여러개의 리이드, (e) 상기 여러개의 본딩 패드와 상기 여러개의 리이드를 전기적으로 접속하는 여러개의 와이어, (f) 상기 반도체 칩 및 상기 여러개의 리이드의 일부분을 봉하여 막은 수지를 포함하는 반도체 장치.(a) a rectangular semiconductor chip having a plurality of bonding pads in a central portion thereof, (b) an organic insulating film covering the surface of the semiconductor chip and having openings in the plurality of bonding pad portions, and (c) an adhesive layer on the insulating film. (d) a plurality of leads bonded to the insulating film on the surface of the semiconductor chip via the adhesive layer, (e) a plurality of wires electrically connecting the plurality of bonding pads and the plurality of leads, (f) the A semiconductor device comprising a semiconductor chip and a resin encapsulating a portion of the plurality of leads. 특허청구의 범위 제1항에 있어서, 상기 패드는 상기 반도체 칩의 긴변 방향으로 일렬로 배치되어 있는 반도체장치.The semiconductor device according to claim 1, wherein the pads are arranged in a line in the long side direction of the semiconductor chip. 특허청구의 범위 제1항에 있어서, 상기 반도체 칩은 메모리 셀 어레이 영역과 주변회로 영역을 가지며, 주변회로 영역은 상기 반도체 칩의 중앙에 위치하는 반도체 장치.The semiconductor device according to claim 1, wherein the semiconductor chip has a memory cell array region and a peripheral circuit region, and the peripheral circuit region is located at the center of the semiconductor chip. 특허청구의 범위 제3항에 있어서, 상기 본딩 패드는 주변 회로 영역의 주변에 배치하여 있는 반도체장치.The semiconductor device according to claim 3, wherein the bonding pads are arranged around a peripheral circuit region. 특허청구의 범위 제3항에 있어서, 상기 주변 회로 영역은 2개의 블록으로 되고, 상기 본딩 패드는 2개의 블록사이에 배치되어 있는 반도체장치.The semiconductor device according to claim 3, wherein the peripheral circuit region is composed of two blocks, and the bonding pads are disposed between the two blocks. 특허 청구위 범위 제1항에 있어서, 상기 유기 절연성 피막은 폴리이미드막인 반도체장치.The semiconductor device according to claim 1, wherein the organic insulating film is a polyimide film. 특허청구위 범위 제1항에 있어서, 상기 유기 절연성피막은 폴리비페닐계 수지막인 반도체장치.The semiconductor device according to claim 1, wherein the organic insulating film is a polybiphenyl resin film. (a) 중앙부에 여러개의 본딩 패드를 갖고, 본딩 패드부 이외의 부분을 무기 절연막으로 덮어진 직사각형의 반도체 칩, (b) 상기 반도체 칩상에 위치하고 상기 여러개의 본딩 패드부에 열림구멍을 갖는 유기 절연성 피막, (c) 상기 유기 절연성 피막상에 위치하는 여러개의 리이드, (d) 상기 반도체 칩과 상기 유기 절연성 피막을 접착하는 제1의 접착제층, (e) 상기 유기 절연성 피막과 상기 여러개의 리이드를 접착하는 제2의 접착제층, (f) 상기 여러개의 리이드와 상기 본딩 패드를 전기적으로 접속하는 여러개의 와이어, (g) 상기 반도체 칩 및 상기 여러개의 리이드의 일부분을 봉하여 막은 수지를 포함하는 반도체장치.(a) a rectangular semiconductor chip having a plurality of bonding pads in the center and covered with an inorganic insulating film in a portion other than the bonding pad portion, and (b) an organic insulating layer having an opening in the plurality of bonding pads and positioned on the semiconductor chip A film, (c) a plurality of leads positioned on the organic insulating film, (d) a first adhesive layer for bonding the semiconductor chip and the organic insulating film, (e) the organic insulating film and the plurality of leads A second adhesive layer to be bonded; (f) a plurality of wires electrically connecting the plurality of leads and the bonding pads, (g) a semiconductor comprising a resin encapsulating and sealing a portion of the semiconductor chip and the plurality of leads Device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880007311A 1987-06-30 1988-06-17 Semiconductor memory device KR960013778B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920012675A KR970004216B1 (en) 1987-06-30 1992-07-16 Semiconductor memory device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62-161333 1987-06-30
JP62161333A JPH0777226B2 (en) 1987-06-30 1987-06-30 Semiconductor device and manufacturing method thereof
JP62234654A JP2567870B2 (en) 1987-09-17 1987-09-17 Semiconductor memory device
JP62-234654 1987-09-17

Publications (2)

Publication Number Publication Date
KR890001183A true KR890001183A (en) 1989-03-18
KR960013778B1 KR960013778B1 (en) 1996-10-10

Family

ID=26487504

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019880007311A KR960013778B1 (en) 1987-06-30 1988-06-17 Semiconductor memory device
KR1019920012675A KR970004216B1 (en) 1987-06-30 1992-07-16 Semiconductor memory device

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1019920012675A KR970004216B1 (en) 1987-06-30 1992-07-16 Semiconductor memory device

Country Status (1)

Country Link
KR (2) KR960013778B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102604724B1 (en) * 2021-12-17 2023-11-22 포스코홀딩스 주식회사 Method for manufacuturing negative electrode material for secondary batteries

Also Published As

Publication number Publication date
KR960013778B1 (en) 1996-10-10
KR970004216B1 (en) 1997-03-26
KR930005170A (en) 1993-03-23

Similar Documents

Publication Publication Date Title
KR920010853A (en) Resin-sealed semiconductor device
KR880001180A (en) Printed Circuit Device
KR930017153A (en) Semiconductor devices
KR960026505A (en) Semiconductor device and manufacturing method thereof
JPS5936249U (en) Flat package for at least one integrated circuit device
KR870010628A (en) Semiconductor devices
KR970067783A (en) Laminated chip package of LOC (lead on chip) type
KR910013444A (en) Electronic device and manufacturing method
KR890013748A (en) Semiconductor devices
KR950004467A (en) Semiconductor device and manufacturing method
KR870009613A (en) Integrated Circuit Chip Mounting & Packaging Assemblies
KR970018433A (en) Connection structure for attaching semiconductor device to substrate
KR940001363A (en) Low Profile Overmolded Pad Array Semiconductor Device and Manufacturing Method Thereof
KR920010872A (en) Multichip Module
KR940008061A (en) Chip Assembly on Substrate and Manufacturing Method Thereof
KR920003480A (en) Semiconductor devices
KR890001183A (en) Semiconductor device
KR900001004A (en) Plastic encapsulated multichip hybrid integrated circuit
KR970077602A (en) A padless leadframe having a tie bar integrally formed with a chip bonding portion and a semiconductor chip package
KR940008060A (en) Semiconductor integrated circuit device
KR930007920Y1 (en) Double package structure having both side thin film
KR920010863A (en) Semiconductor device
KR960005965A (en) Semiconductor devices
KR970063590A (en) Chip scale package with tap tape
JPS62226636A (en) Plastic chip carrier

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101007

Year of fee payment: 15

EXPY Expiration of term