KR880004679A - Pulse Processing Circuit for Video Processing - Google Patents

Pulse Processing Circuit for Video Processing Download PDF

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Publication number
KR880004679A
KR880004679A KR870010087A KR870010087A KR880004679A KR 880004679 A KR880004679 A KR 880004679A KR 870010087 A KR870010087 A KR 870010087A KR 870010087 A KR870010087 A KR 870010087A KR 880004679 A KR880004679 A KR 880004679A
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KR
South Korea
Prior art keywords
pulse
shaping circuit
circuit
gate
output
Prior art date
Application number
KR870010087A
Other languages
Korean (ko)
Other versions
KR910002777B1 (en
Inventor
하지메 스미요시
Original Assignee
아오이 죠이치
가부시끼 가이샤 도시바
오시마 고다로
도시바 오디오.비이오 엔지니어링 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시끼 가이샤 도시바, 오시마 고다로, 도시바 오디오.비이오 엔지니어링 가부시끼 가이샤 filed Critical 아오이 죠이치
Publication of KR880004679A publication Critical patent/KR880004679A/en
Application granted granted Critical
Publication of KR910002777B1 publication Critical patent/KR910002777B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
    • H04N5/185—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit for the black level

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Details Of Television Scanning (AREA)
  • Television Receiver Circuits (AREA)

Abstract

내용 없음No content

Description

비디오처리용 펄스성형회로Pulse Processing Circuit for Video Processing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예를 나타낸 블록도.1 is a block diagram showing an embodiment of the present invention.

제2도는 제1도에 도시된 펄스성형회로를 구체적으로 나타낸 회로도.2 is a circuit diagram showing in detail the pulse shaping circuit shown in FIG.

제3도는 제2도에 도시된 펄스성형회로의 각부전위파형을 나타낸 도면.FIG. 3 is a diagram showing respective potential waveforms of the pulse shaping circuit shown in FIG.

제4도는 수직펄스발생기의 일례를 나타낸 도면.4 shows an example of a vertical pulse generator.

제5도는 게이트펄스성형회로를 나타낸 도면.5 shows a gate pulse shaping circuit.

제6도 및 제7도는 제5도에 도시된 게이트펄스성형회로의 동작을 설명하는 각부전위파형도.6 and 7 are angular potential waveform diagrams illustrating the operation of the gate pulse shaping circuit shown in FIG.

제8도는 밝기조정회로를 나타낸 도면이다.8 is a diagram showing a brightness adjustment circuit.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10, 21 : 입력단자 11 : 게이트펄스성형회로10, 21: input terminal 11: gate pulse shaping circuit

12 : 무신호보상회로 20 : 수직발진기12: no signal compensation circuit 20: vertical oscillator

22 : 펄스성형회로 23 : 가산기22 pulse forming circuit 23 adder

25 : 밝기조정회로 30 : 다운카운터25: brightness adjustment circuit 30: down counter

31, 32 : 게이트회로 a : 수평동기신호31, 32: gate circuit a: horizontal synchronous signal

a0, a1 : 게이트펄스 a2 : 보상게이트펄스a0, a1: gate pulse a2: compensation gate pulse

I11, I51, I52 : 정전류원 b1, b2 : 영상신호I11, I51, I52: constant current source b1, b2: video signal

2b : 수직펄스 VL41 : 밝기조정볼륨2b: Vertical pulse VL41: Brightness adjustment volume

SW41 : 스위치 COM1∼COM2 : 전압비교회로SW41: Switch COM1 to COM2: Voltage comparator

CM1, CM2 : 전류미러회로CM1, CM2: Current Mirror Circuit

Claims (2)

비디오신호의 동기신호를 기준으로하여 그 동기신호보다 더 지연된 게이트펄스를 성형해 주는 레이트펄스성형회로(11)를 구비하고 있는 비디오처리용 펄스성형회로에 있어서, 해당 펄스성형회로는 수직펄스발생수단으로 부터의 수직펄스를 이용해서 수직귀선기간의 소정기간내에 수평동기신호를 제거한 펄스를 발생해 주는 보상펄스성형회로(22)와, 상기 게이트펄스성형회로(11)로 부터의 게이트펄스와 보상펄스성형회로(22)로 부터의 펄스와의 가산출력을 밝기조정펄스로서 출력해 주는 출력수단(23)을 구비하고 있음을 특징으로 하는 비디오처리용 펄스성형회로.A pulse processing circuit for video processing comprising a rate pulse shaping circuit 11 for shaping a gate pulse which is delayed more than the synchronizing signal on the basis of a synchronous signal of a video signal, wherein the pulse shaping circuit is a vertical pulse generating means. The compensation pulse shaping circuit 22 generates a pulse from which the horizontal synchronizing signal is removed within a predetermined period of the vertical retrace period using the vertical pulses from the gate pulse and the gate pulse and the compensation pulse from the gate pulse shaping circuit 11. And an output means (23) for outputting the addition output with the pulse from the shaping circuit (22) as a brightness adjustment pulse. 제1항에 있어서, 출력수단(23)은 가산출력과 수평블랭킹펄스의 논리적으로 되는 펄스를 출력하도록 된 것을 특징으로 하는 비디오처리용 펄스성형회로.2. The pulse shaping circuit for video processing according to claim 1, wherein the output means (23) is configured to output a pulse which is logical of the addition output and the horizontal blanking pulse. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870010087A 1986-09-11 1987-09-11 Video processing pulse shaping circuit KR910002777B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP61-214282 1986-09-11
JP61214282A JPH0728378B2 (en) 1986-09-11 1986-09-11 Pulse shaping circuit for video processing
JP214282 1986-09-11

Publications (2)

Publication Number Publication Date
KR880004679A true KR880004679A (en) 1988-06-07
KR910002777B1 KR910002777B1 (en) 1991-05-04

Family

ID=16653152

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870010087A KR910002777B1 (en) 1986-09-11 1987-09-11 Video processing pulse shaping circuit

Country Status (4)

Country Link
JP (1) JPH0728378B2 (en)
KR (1) KR910002777B1 (en)
DE (1) DE3730623A1 (en)
GB (1) GB2197562B (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935542B2 (en) * 1976-11-18 1984-08-29 松下電器産業株式会社 DC component regeneration device for television receivers
US4410907A (en) * 1981-11-16 1983-10-18 Rca Corporation Burst gate keying and back porch clamp pulse generator
JPS59218080A (en) * 1983-05-25 1984-12-08 Matsushita Electric Ind Co Ltd Pedestal level clamp circuit

Also Published As

Publication number Publication date
JPS6369382A (en) 1988-03-29
GB2197562A (en) 1988-05-18
DE3730623A1 (en) 1988-03-17
GB2197562B (en) 1990-10-10
GB8721281D0 (en) 1987-10-14
KR910002777B1 (en) 1991-05-04
JPH0728378B2 (en) 1995-03-29
DE3730623C2 (en) 1992-11-05

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