KR880003597Y1 - Computer terminal device - Google Patents

Abstract

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Description

Attribute signal control circuit of computer terminal equipment

1 is a circuit diagram showing a circuit configuration according to the present invention.

2 is a frame structure diagram of data to be input to the circuit shown in FIG.

3 is a timing chart for the circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

1, 3: Latch circuit 2: Character generator

4: Shift register NR ₁ , NR ₂ : Noah gate

AD ₁ to AD ₃ : AND gate OR ₁ to OR ₃ : Oagate

EX ₁ : exclusive oA circuit

The present invention relates to an attribution signal control circuit of a computer terminal device, and more particularly, to an attribution signal control circuit of a computer terminal device capable of performing attribution signal processing without the use of an attribution RAM.

In general, a monitor device is one of the most widely used terminal devices for data output of a microcomputer. The monitor device is configured to display (display) output data output from the microcomputer, for example, as a figure or a character.

In addition, when displaying characters on the monitor screen as described above, in order to perform various character display, attribute RAM (Independent of RAM) or parallel input and output type LATCH (PIO) is used. By doing this, attribute control such as inverting a character or underlining a character can be performed.

However, in the case where the attribute processing is performed using the conventional attribute RAM, the attribute character is written in the attribute RAM instead of the video RAM, so that the use range of the video RAM can be extended. As the separate RAM is used, the same amount of RAM as the video RAM must be used, and additional latch circuits for matching the timing are required, which leads to complicated circuits and an increase in price. Even in the case of using the attribute control, there is a problem that the price increases compared to the effect.

Accordingly, the present invention has been devised to solve the above-mentioned problem. Instead of using attribute RAM and PIO, a specific bit of the ASCII code is a character in the ASCII code that is generally used to display a character on a monitor screen. In case of not displaying the value, it is considered to be low level. When a certain bit of this ASCII code becomes low level, the attribute data value is stored in the latch circuit through the video RAM, and the data value stored in this latch circuit is The purpose of the subsequent attribute control is to simplify the attribute control circuit and reduce the production cost.

Hereinafter, the configuration, operation, and effects of the present invention will be described in detail with reference to the accompanying drawings.

The subject innovation is in the data lines (D ₀ ~ D _6), character generator 2 and shift register 4 are sequentially connected to the character generator, the latch circuit (1) to the data lines (D ₀ ~ D ₃₎ the input terminal (d ₀ ~ d ₃₎ is deeoteo line (D _5, D _6), in addition as soon connected, NOR gate (NR ₁₎ and the character clock to another terminal signal (CK ₁₎ is applied to the aND gate (AD ₁₎ via the other hand, that the clock input terminal of said latch circuit (1) connected to the data lines (D _7), the one input terminal of the latch circuit 3, to which the dot clock signal (CK ₂₎ to the clock input terminal (d ₁ ) is connected to the output terminal Q ₀ of the latch circuit 1, and the other input terminal is connected to the latch circuit 1 via an AND gate AD ₂ through which a signal A is input to the other input terminal. the output terminal (Q ₁₎ of Iowa gate (OR ₁₎ a is connected, wherein the gate Iowa said NOR gate (NR ₁₎ and has one input connection point of the aND gate (AD ₁₎ connected to a (OR ₁₎ The shift gate connected to the output terminal of the NR ₂ is connected to the output terminal of the NR ₂ via a shift register OR ₂ through which the shift / loud signal CK ₃ is applied to one of the shift registers. (4) clear terminal ( Is connected to the output terminal (Q ₂ ) of the latch circuit (1), the input terminal (d ₂ ) of the latch circuit (3) is connected via an AND gate (AD ₃ ) to which a signal (B) is applied to one input terminal. The input terminal d ₃ of the latch circuit 3 is connected to the output terminal Q ₃ of the latch circuit 1, and one input terminal is connected to the output terminal Q ₂ of the latch circuit 3. An output terminal via an ORA gate OR ₃ connected to an output terminal of the shift register 4 and an exclusive OR circuit EX ₁ connected to another output terminal Q ₃ of the latch circuit 3 in order. (OUTPUT) is connected.

FIG. 1 is a circuit diagram showing a circuit configuration according to the present invention having the above configuration, and FIG. 2 is ASCII coded data to be input to the data lines D ₀ to D ₇ of the circuit diagram shown in FIG. of the drawing place by showing the frame structure, the second even data (D ₀ ~ D _7; reference symbol for each data for convenience are shown as data lines and the same code is to be the data is input), data (D ₅ of, D ₆₎ the data (D ₀ ~ a characteristic bit indicating a feature of D ₆₎ the data (D _5, D ₆₎ which any of "1" is the data (D ₀ ~ D _6, if one or more of) the character information means and intended to the data (D _5, D ₆₎ If all is "0", the data (D ₀ ~ D ₃₎ means that the attribute data indicating the attribute of the character to the data (D ₇₎ is It is irrelevant to the present invention and the description is omitted.

That is, in FIG. 1, when the data D ₅ and D ₆ are not all "0", that is, not in the attribute mode, the data ((D ₀ to D ₆ ) is input to the character generator 2 as character information. bar, at this time, the low level is output from the NOR gate (NR ₁₎ is presented to the aND gate (AD ₁₎ enter the aND gate is also low level output of the (AD ₁₎ as in, followed by a low level output is latched is presented circuit By being applied to the clock input terminal of (1), the latch circuit 1 has all of its outputs at the low level (since no data was initially latched), while the character generator 2 inputs the data D _0. ~ D ₆₎ to generate a patterned character information corresponding to there is transmitted to the shift register (4) which was output to the parallel input in series, and wherein said NOR gate (input low level of from NR ₁₎ and Iowa gate Noah gate (NR ₂ by low-level input from (OR ₁ ) ) Output becomes high level, and this high level output is then passed through the oragate OR ₂ to the clear terminal of the shift register 4. In the shift register 4, the parallel character information input from the character generator 2 is input to the dot clock signal CK ₄ (the dot clock signal CK ₄ is input to the latch circuit 3). Synchronized with the dot clock signal CK ₂ ] and the shift / loud signal CK ₃ to be serialized and sequentially output.

Subsequently, serialized character information sequentially output from the shift register 4 is applied to the oragate ₃ , wherein the output level output from the output terminals Q ₀ to Q ₃ of the latch circuit 1 is output. Since all of these are low level, the output levels output from the output terminals Q ₂ and Q ₃ of the latch circuit 3 also become low levels. Therefore, the character information output from the shift register 4 is output as is. Will be output to (OUTPUT).

On the other hand, during some clock time in which all of the data D ₅ and D ₆ of the input data D ₀ to D ₆ become low level, that is, while the attribute control data is input (after the attribute control data is input), In the character data is input), since the data (D ₅ , D ₆ ) are all low-level is the control data for the system, the character information is not output from the character generator (2), the data (D ₅ , D 6) ₆ ) are all at low level, so the output of the noble gate NR ₁ is at high level. [Fig. 3 (3-2)] The third level (3-) which is the character clock signal CK ₁ at the other input terminal. 1) Since the signal is inputted to the AND gate AD ₁ to which the signal is input, the signal of FIG. 3-3 is outputted from the output terminal of the AND gate AD ₁ to the clock signal input terminal of the latch circuit 1. To be authorized. In other words, the input data D ₀ to D ₃ are latched in the latch circuit 1.

On the other hand, in the attribute data D ₀ to D ₃ inputted from the video RAM (not shown) to the data lines D ₀ to D ₃ when the data D ₅ and D ₆ are all at the low level, Data D ₀ is an attribute signal indicating a blinking attribute, data D ₁ is used as an empty signal, data D ₂ is underlined, and data D ₃ is used as an attribute signal indicating an inversion attribute.

First, when the input data D ₀ to D ₆ input from the video RAM is "1000000", that is, the data for executing the flickering attribute, the data "1000" of the input data "1000000" is an AND gate ( When the output of AD ₁ becomes high level, the latch is latched to the latch circuit 1 so that Q ₀ is "1" from the output terminals Q ₀ to Q ₃ of the latch circuit 1, and the rest is "0". "1000" data is output. Therefore, a low level (i.e., "0") is inputted to the input terminals d ₂ and d ₃ of the latch circuit 3 so that "0" data is output to the output terminal thereof, and to the output terminal of the AND gate AD ₂ . The clock signal A indicating the flickering ratio is outputted from the output stage of the NOA gate NR ₁ from the moment when the input data D ₀ to D ₆ are changed from the attribute control data to the normal character data. As the low level is outputted, the clock signal A is inputted to the oragate OR ₂ to which the shift / load signal CK ₃ is applied to the other input terminal.

On the other hand, the shift register 4 outputs parallel input data as serial output data, that is, for example, when the data input to the shift register 4 is parallel data of 8 bits, the shift / loud stage S When the shift / loud signal CK ₃ (FIG. 3-7) input to L / L becomes low level, the 8-bit parallel input data is routed to the shift register 4, and then shifted. When the low signal reaches a high level, the bit clock signal CK ₄ (not shown) is output by 1 bit, and the period of the clock signal A is a shift / loud signal CK. _It is set considerably longer than the period of ₃ ).

Accordingly, the clear terminal of the clock signal (A) and a shift / low DE signal (CK ₄₎ the type and the Iowa gate (OR _2), the Iowa gate (OR _2), the output signal shift register (4) of ( ), Whether or not the shift register 4 is cleared is controlled by the clock signal A. FIG. That is, for example, if 10 shift / loud signal CK ₃ pulses are generated per pulse of the clock signal A, from the oragate OR _{2 while the} clock signal A is at a high level. Since the high level is always output and the shift register 4 is not cleared, the character information is normally output from the shift register 4, at which time from the output terminals Q ₂ and Q ₃ of the latch circuit 3. Since the low level is output, the character information output from the shift register 4 is output to the output terminal OUTPUT.

On the other hand, whenever the shift / loud signal CK ₄ becomes low level while the clock signal A is low level, the shift register 4 is cleared so that the shift / loud signal CK ₄ becomes low level. When the data is not loaded into the shift register 4, which is configured to load the input data, it is impossible to output any data to the output stage. Accordingly, when the flicker attribute data (Q ₀ to Q ₃ is " 1000 ") is latched in the latch circuit 1, the characters displayed on the monitor screen later flicker according to the clock signal A. FIG.

Next, a description will be given of a blank attribute control in which a space is left blank without displaying a character to be displayed on a monitor screen.

When the blank attribute processing is performed [Fig. 3 (3-5)], the input data Q ₀ to Q ₆ are inputted as "100000". In this case, the character generator is operated as in the case of the blink attribute processing. While (2) becomes inoperative, latch circuit 1 latches "100" so that "100" is output to output terminals Q ₀ to Q ₃ until another attribute control signal is input next. do. On the other hand, as in the above case, immediately after the attribute control signal is input, the data for the character processing, that is, at least one of D ₅ and D ₆ , is data of input data (D ₀ to D ₆ ). Is input and the character generator 2 performs normal character processing.

Subsequently, when the data “100” is output from the output terminals Q ₀ to Q ₃ of the latch circuit 1 as described above, the low level (from the AND gate AD ₂ and the NO gate NR ₁ , respectively). Since the character data is input after the attribute data is input as described above, the high level output output from the output terminal Q ₁ of the latch circuit 1 is low through the noar gate NR ₂ . Inverted to the level and applied to the OR gate OR ₂ , in this case, during the blinking attribute processing, the clock signal A is in the same state as the high level, and is shifted from the character generator 2 to the shift register 4. Whenever parallel input data is loaded, it is cleared. Therefore, since the data is not output from the shift register 4 and the low level is also output from the output terminals Q ₂ and Q ₃ of the latch circuit 3, the position of the corresponding character is blank on the monitor screen. blank).

Subsequently, "10000" is input to the input data Q ₀ to Q ₆ at the time of the underscore attribute processing (FIG. 3-6). In this case, the output terminal of the latch circuit 1 is operated by the above operation. "10" is outputted from Q ₁ ~ Q ₃ ).

Subsequently, the high level output output from the output terminal Q ₂ of the latch circuit 1 is input to the AND gate AD ₃ to which the signal B is applied to another input terminal, where the signal B is underlined. When the corresponding position, for example, the character display is 13 scan lines, the high level is displayed when the last scan line is displayed. Therefore, in this case, when the signal B becomes high level, the high level is output to the output terminal Q ₂ of the latch circuit 3, while the other output terminals Q ₀ , Q ₁ , Q of the latch circuit 1 are output. ₃ ) are all at the low level, so the operation of other parts is the same as in normal character processing. The patterned character information understood by the bamboo character generator 2 is sequentially input to the oragate 3 through the shift register 4.

Accordingly, when the signal B is at a low level, that is, up to 12 scan lines of the 13 scan lines, the low level is output from the output terminals Q ₂ and Q ₃ of the latch circuit 3, so that the signal B is at a low level. Similarly, the character information output from the shift register 4 is output as it is to the output terminal OUTPUT, while the signal B becomes high level, that is, the output terminal of the latch circuit 3 at the 13th scan line. The output data from Q ₂ , Q ₃ ) becomes "1" and "0", respectively, so that "1111111" is output to the output terminal OUTPUT, and a line is drawn on the monitor screen by this signal.

In addition, when the inversion attribute control data is input to the input data lines D ₀ to D ₆ (Fig. 3 (3-4)), the output terminals Q ₀ to Q of the latch circuit 1 by the above operation. ₃ ) is outputted from the output terminal Q ₃ of the latch circuit 3, and thus a high level (1) is outputted to the exclusive OR circuit EX ₁ . The other part operates as in the normal character processing.

Therefore, in the exclusive OR circuit EX ₁ , the operation of the character information output from the shift register 4 and the data “1” output from the latch circuit 3 is performed. When " 100111 " is output, " 1011000 " is outputted to the output terminal OUTPUT, so that the characters displayed on the monitor screen are displayed after changing the contrast.

In addition, the return from the attribute control mode to the normal character processing mode is performed by inputting "0" into the input data D ₀ to D ₆ .

As described above, according to the present invention, instead of using a separate attribute RAM, the video RAM used for character processing is used to execute attribute control, and when the same attribute control is performed, attribute processing is performed for each character process. In order to avoid the need to receive the same attribute data again, the attribute control circuit can be simplified and the video RAM can be more efficient.

Claims (1)

Data lines (D ₀ ~ D _6), character generator 2 and in the shift register 4 are sequentially connected to the character generator, the input terminals of the data lines (D ₀ ~ D _3), the latch circuit (1) in the In addition to the (d ₀ to d ₃ ) connected to the data lines D ₅ and D ₆ , an AND gate AD ₁ to which the character clock signal CK ₁ is applied to the other terminal of the NOA gate NR ₁ is provided. While the clock input terminal of the latch circuit 1 is connected, one input terminal d ₁ of the latch circuit 3 to which the dot clock signal CK ₂ is applied to the clock input terminal is connected to the data line D ₇ . The output terminal Q ₀ of the latch circuit 1 is connected to an output terminal Q ₂ of the latch circuit 1 via an AND gate AD ₂ through which an signal A is input to the other input terminal. The OR gate OR ₁ connected to Q ₁ ) is connected, and one input terminal is connected to the NOA gate NR ₁ and the AND gate AD ₁ , and the OR gate OR _{1 is} connected to the output terminal. The connected NOR gate (NR ₂₎ is connected, a NOR gate (NR ₂₎ output terminal via the Iowa gate (OR ₂₎ to which the shift / low DE signal (CK ₃₎ to the input terminal of the shift register (4) Clear terminal ( Is connected to the output terminal (Q ₂ ) of the latch circuit (1), the input terminal (d ₂ ) of the latch circuit (3) is connected via an AND gate (AD ₃ ) to which a signal (B) is applied to one input terminal. The input terminal d ₃ of the latch circuit 3 is connected to the output terminal Q ₃ of the latch circuit 1, and one input terminal is connected to the output terminal Q ₂ of the latch circuit 3. An output terminal via an ORA gate OR ₃ connected to an output terminal of the shift register 4 and an exclusive OR circuit EX ₁ connected to another output terminal Q ₃ of the latch circuit 3 in order. An attribute signal control circuit for a computer terminal device, characterized in that the (OUTPUT) is connected.