JPH0950268A - Display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the disturbance in the screen of a display module by temporarily stopping the output of a scanning signal FILM' at the time of rising a display system by executing a system reset. SOLUTION: An AND gate circuit is held closed to prevent the output of the scanning signal FILM' until the end of the initialization of memory access function of a large capacity disposed in a timing controller 6 by a CPU circuit and various kinds of registers 4, such as a smart address register, display duty register and display start raster address register. The AND gate circuit is opened to start the output of the section signal FILM' when the initialization of the respective registers 4 end and the initialization end signal is outputted from the CPU circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display system used as a display device of various electronic devices such as a display device of a computer and a display device of a word processor.

[0002]

2. Description of the Related Art In a display system used as an output device such as a computer or a word processor, various techniques have been conventionally proposed in order to prevent display flicker. For example, in the “display control device” disclosed in Japanese Patent Laid-Open No. 04-216592, even if the drive voltage of the display control device is lowered, a screen in which a graphic displayed on the LCD display device and a character are combined is displayed. Avoid flicker. Further, in the "LCD gradation display control device" disclosed in Japanese Patent Laid-Open No. 01-273094, the frame rate modulation is performed by synchronizing odd frames of a specific number or more to prevent the display characteristics from being deteriorated.

[0003]

However, the general display control device including each of these display control devices has the following problems. That is, the normal display system outputs the VRAM address data MA and the raster address data RA from the timing controller 101 as shown in FIG.
The font data corresponding to each character stored in 2 is designated, the font data is output from the character generator 103 in raster units, and this is taken in as character data MD. Then, the timing controller 101
To display data LU0− from the character data MD
3, LD0-3 are generated, and the LCD module 10
Scan signal F while supplying to the column driver 105 of No. 4
LM, scan signal M, scan signal CL1, and scan signal C
L2 and L2, and generate them in the column driver 105
To the common driver 106, and the contents of each frame stored in the frame buffer 102 are displayed on the LCD panel 107 which constitutes the LCD module 104.

In this case, the timing controller 1
The FLM signal generation circuit in 01 is reset by the reset signal input through the OR gate circuit 110 when the system is reset and the system is started up as shown in FIG. 5, and thereafter, every time the scanning signal CL1 is input. , The count value output from the counter circuit 111 by the comparator circuit 112 and the display duty set in the latch circuit 113 each time the count value output from the counter circuit 111 that counts up reaches a specified value. When a match with the value is detected, a reset signal is output from the AND gate circuit 114, and the counter circuit 111 is reset. At this time, the inverting input type AND gate circuit 115 detects this, and the AND gate circuit 116 and the two D-type flip-flop circuits 11 are detected.
The scanning signal FLM is generated by the combinational circuit constituted by 7, 118 and is supplied to the LCD module 104.

Therefore, when the system is reset, the CPU
When the circuit performs initialization (initialization) of a large-capacity memory access function provided in the timing controller 101 and various registers such as a start address register, a display duty register, and a display start raster address register, the initialization process is performed. Before the end, the scanning signal FLM is output from the FLM signal generating circuit.
Is automatically output and the screen of the LCD panel 107 that constitutes the LCD module 104 is disturbed. Therefore, as a method for solving such a problem, a dedicated reset circuit for system resetting the FLM signal generating circuit in the timing controller 101 and a dedicated reset circuit for system resetting other circuits in the timing controller 101 are provided. When the system is reset, the dedicated reset circuits are used to operate various registers such as a large-capacity memory access function provided in the timing controller 101, a start address register, a display duty register, and a display start raster address register. It is also possible to reset the FLM signal generating circuit after the initialization.

However, in this case, two dedicated reset circuits must be prepared, and that much is required.
There has been a problem that the circuit scale becomes large and the number of control lines increases to increase the occupied area of the circuit. Regarding this point, the above-mentioned Japanese Patent Laid-Open No. 04-216
Nothing is described in the "display control device" disclosed in Japanese Patent No. 592 or the "LCD gradation display control device" disclosed in Japanese Patent Laid-Open No. 01-273094. In view of the above circumstances, the present invention, when the system is reset and the system is started up, stops the driving of the display module side until initialization of a portion required for initialization provided in the timing controller is completed, An object of the present invention is to provide a display system capable of starting driving of the display module after initialization is completed and thereby preventing the screen of the display module from being disturbed immediately after resetting.

[0007]

In order to achieve the above object, the present invention generates various scanning signals by a timing controller and, together with these scanning signals, displays the contents of an image to be displayed. In the display system that supplies data to the display module and displays it on the screen,
Until the initialization of the timing controller is completed, the output of the scan signal specified in advance among the scanning signals generated by the timing controller is stopped, and the output is stopped after the initialization of the timing controller is completed. It is characterized in that the output of the scanning signal is started to prevent the screen of the display module from being disturbed at the time of initialization.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a block diagram showing an example of a form of a display system according to the present invention. In the display system 1 shown in this figure, the contents of the frame to be displayed are written and the input VRAM address data MA
A frame buffer 2 for outputting the character data written in the address corresponding to
A character generator 3 for outputting character data MD corresponding to the input character data and the input raster address data MA, various registers 4 and an FLM 'generation circuit 5, and a CPU circuit (not shown). Processing for generating the VRAM address data MA and the raster address data MA on the basis of the control signal output from the controller, etc. and controlling the frame buffer 2 and the character generator 3 to fetch the character data MD. The character data M
Processing for generating display data LU0-3, LD0-3 based on D, scanning signal FLM ′, scanning signal M, scanning signal C
A timing controller 6 for performing processing for generating L1 and a scanning signal CL2, and an output from the timing controller 6 based on the scanning signal FLM ′, the scanning signal M, the scanning signal CL1, and the scanning signal CL2 output from the timing controller 6. Display data LU0-3,
The LCD module 7 which takes in LD0-3 and displays an image is provided.

Then, from the timing controller 6 to V
RAM address data MA and raster address data R
A is output, font data corresponding to each character data stored in the frame buffer 2 is designated, this is fetched in raster units, and display data LU0-
3, LD0-3 are generated, and the scanning signal FLM 'is generated.
, Scan signal M, scan signal CL1, and scan signal CL2
Are generated and supplied to the LCD module 7, and the contents of each frame stored in the frame buffer 2 are displayed on the LCD module 7.

In this case, the LCD module 7 has the scanning signal F output from the timing controller 6.
A common driver 8 that generates a common drive voltage based on LM ′, the scan signal M, and the scan signal CL1, and display data LU0− output from the timing controller 6.
3, LD0-3, a scan signal FLM ', a scan signal M, a scan signal CL1, and a scan signal CL2, and a column driver 9 for generating a column drive voltage, and a plurality of pixels arranged in a matrix. The LCD panel 10 displays an image by turning on / off each of the pixels based on a common drive voltage output from the driver 8 and a column drive voltage output from the column driver 9.

Then, the scanning signal FLM 'output from the timing controller 6 and indicating the head line of each display frame, the scanning signal M necessary for AC driving the LCD panel 10, and the display on the column driver 9 are displayed. Scan signal CL1 required for latching data LU0-3, LD0-3 and scan signal serving as a shift clock required for shifting display data LU0-3, LD0-3 latched by the column driver 9. Based on CL2, the display data LU0-3, LD0-3 output from the timing controller 6 is fetched, and the image represented by the display data LU0-3, LD0-3 is displayed on the screen.

Further, the FLM 'generation circuit 5 in the timing controller 6 outputs an OR gate circuit 11 which takes the logical sum of the reset signals RESET input as shown in FIG. 2 and a reset signal output from the OR gate circuit 11. When a write signal WR is output from the 8-bit counter circuit 12 that is reset each time the scan signal CL1 is input and the CPU circuit outputs the write signal WR, the write signal WR is output together with the write signal WR. An 8-bit latch circuit 13 for fetching and latching display duty data indicating the number of lines in one frame, a value of the display duty data latched by the latch circuit 13, and a count result output from the counter circuit 12 , And when they match, generate a match signal and reset it. 8-bit comparator circuit 14 which outputs as an input signal and an AND gate circuit 15 which supplies a reset signal output from the comparator circuit 14 to the OR gate circuit 11 when the scanning signal CL1 is input. It has and.

Further, the FLM 'generation circuit 5 in the timing controller 6 is an inverting input type AND gate which generates a frame head signal each time the count result output from the counter circuit 12 becomes "0". Circuit 1
6 and the scanning signal CL1 as shown in FIG. 3B, the frame head signal output from the AND gate circuit 16 is taken in and the scanning signal FLM is obtained as shown in FIG. Output of the scanning signal FLM output from the AND gate circuit 17 based on the generated AND gate circuit 17 and the system clock signal MCLK and the inverted system clock signal MCLK for operating the timing controller 6 as shown in FIG. Two D-type flip-flop circuits 18 and 19 for adjusting timing
When the reset signal RESET is input, the reset signal is reset, the CPU circuit completes initialization of the registers 4 and the like provided in the timing controller 6, and a write signal is output from a synchronization circuit (not shown). A latch circuit 20 for latching an initialization end signal output from the CPU circuit when output,
When the latch circuit 20 latches the initialization end signal, the D-type flip-flop 19
(D) of FIG. 3 by taking in the scanning signal FLM output from
The AND gate circuit 21 for generating the scanning signal FLM ′ is provided after the Nth frame as shown in FIG.

Then, when the system is reset and the system is started up, the counter circuit 12 is reset, and every time the scanning signal CL1 is input, it is counted, and the count value obtained by this counting operation is The count value of the count circuit 12 is reset to "0" each time the value of the display duty data output from the CPU circuit matches, and the scan signal FLM is generated. After that, when the initialization completion signal is output from the CPU circuit, the AND gate circuit 21 is set in the passing state to generate the scanning signal FLM ′ from the scanning signal FLM, and the scanning signal FLM ′ is supplied to the LCD module 7.

Thus, in this embodiment, the CP
Until the initialization of the large-capacity memory access function provided in the timing controller 6 and the various registers 4 such as the start address register, the display duty register, and the display start raster address register by the U circuit is completed, the AND gate circuit 21 is operated. In the closed state, the scanning signal FLM 'is not output,
After the initialization of each register 4 is completed, the C
When the initialization end signal is output from the PU circuit, the AND gate circuit 21 is opened to start the output of the scanning signal FLM '. Therefore, when the system is reset and the system is started up, the timing controller The driving of the LCD module 7 side is stopped until the initialization of the portion requiring initialization in 6 is completed, and after the initialization is completed, the LC
The driving of the D module 7 is started so that the screen of the LCD module 7 can be prevented from being disturbed immediately after resetting.

Further, in the above-mentioned form example, FL
When the reset signal RESET is input to the M'generation circuit 5, the scanning signal FLM 'becomes non-active, but in this case as well, after the resetting of each register 4 in the timing controller 6 is completed, the CPU circuit Then, the output of the scanning signal FLM ′ can be started by outputting the initialization end signal again. Further, in the above-described embodiment, when the CPU circuit outputs the initialization end signal, the synchronization circuit outputs the write signal so that the latch circuit 20 latches the initialization end signal.
As such a synchronizing circuit, an address is assigned by the CPU circuit, and a circuit that outputs a write signal in synchronization with a write pulse output from the CPU circuit or the like is used to easily generate a write signal. This makes it possible to minimize the circuit changes other than the timing controller 6. Further, in the above-described embodiment, the scanning signal FLM generated by the timing controller 6 is gated,
Although the scanning signal FLM ′ is generated, for the scanning signal M, the scanning signal CL1, the scanning signal CL2, etc.,
You may make it perform the same process.

[0017]

As described above, according to the present invention, when the system is reset to start up the system,
The drive of the display module is stopped until the initialization of the part that requires initialization in the timing controller is completed, and after the initialization is completed, the drive of the display module is started. In, it is possible to prevent the screen of this display module from being disturbed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a form of a display system according to the present invention.

FIG. 2 is a circuit showing a detailed configuration example of the FLM ′ signal generation circuit shown in FIG.

3 (a) to 3 (d) are timing charts showing an operation example of the FLM 'signal generating circuit shown in FIG.

FIG. 4 is a block diagram showing an example of a generally known general display system.

5 is a circuit showing a detailed configuration example of an FLM signal generation circuit provided in the timing controller shown in FIG.

[Explanation of symbols]

1 display system, 2 frame buffer, 3 character generator, 4 register, 5 FLM 'signal generation circuit, 6
Timing controller, 7 LCD module, 8
Common driver, 9 column driver, 10 LCD panel

Claims (1)

[Claims] 1. A display system in which various scanning signals are generated by a timing controller, and together with these scanning signals, display data indicating the content of an image to be displayed is supplied to a display module for screen display. Until the initialization of the timing controller is completed, the output of the scanning signal designated in advance among the scanning signals generated by the timing controller is stopped, and the output is stopped after the initialization of the timing controller is completed. A display system characterized in that the output of a scanning signal is started so that the screen of the display module is not disturbed at the time of initialization.